公开(公告)号：WO2010080735A1

公开(公告)日：2010-07-15

申请号：PCT/US2010/020059

申请日：2010-01-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  MUKHERJEE, Maharaj ,  CULP, James, A. ,  LAI, Kafai ,  MANSFIELD, Scott, M. ,  ROSENBLUTH, Alan, E.

Inventor： MUKHERJEE, Maharaj ,  CULP, James, A. ,  LAI, Kafai ,  MANSFIELD, Scott, M. ,  ROSENBLUTH, Alan, E.

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5λ/NA to distance ROI2 when the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROM to ROI2 are smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy.

Abstract translation: 提供了一种用于在用于制造半导体集成电路的光掩模的设计中对光刻工艺进行建模的方法，更具体地说，用于模拟中间范围闪光效应。 对于当点扩散函数具有根据预定标准缓慢变化的斜率时，从大约5λ/ NA到距离ROI2的第一ROI1的影响区域（ROI），至少在从ROM到 在计算SOCS卷积之前，ROI2被平滑。 该方法提供了一种用于以足够的精度模拟中等范围闪光效果的快速方法。

公开(公告)号：WO2009061527A1

公开(公告)日：2009-05-14

申请号：PCT/US2008/061196

申请日：2008-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  MUKHERJEE, Maharaj ,  GRAUR, Ioana, C. ,  ROSENBLUTH, Alan, E.

Inventor： MUKHERJEE, Maharaj ,  GRAUR, Ioana, C. ,  ROSENBLUTH, Alan, E.

IPC: G03F1/14 ,  G03F7/20

CPC classification number: G06K9/036 ,  G03F7/70441

Abstract: Embodiments of the present invention provide a method of performing printability verification of a mask layout. The method includes creating one or more tight clusters; computing a set of process parameters associated with a point on said mask; comparing said set of process parameters to said one or more tight clusters; and reporting an error when at least one of said process parameters is away from said one or more tight clusters.

Abstract translation: 本发明的实施例提供了一种执行掩模布局的可印刷性验证的方法。 该方法包括创建一个或多个紧密簇; 计算与所述掩模上的点相关联的一组过程参数; 将所述一组过程参数与所述一个或多个紧密簇进行比较; 并且当至少一个所述过程参数远离所述一个或多个紧密簇时报告错误。

公开(公告)号：WO2008057996A2

公开(公告)日：2008-05-15

申请号：PCT/US2007/083441

申请日：2007-11-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LAI, Kafai ,  ROSENBLUTH, Alan, E. ,  GALLATIN, Gregg, M. ,  MUKHERJEE, Maharaj

Inventor： LAI, Kafai ,  ROSENBLUTH, Alan, E. ,  GALLATIN, Gregg, M. ,  MUKHERJEE, Maharaj

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A fast method of verifying a lithographic mask design is provided wherein catastrophic errors (432) are identified by iteratively simulating and verifying images for the mask layout using progressively more accurate image models (411), including optical and resist models. Progressively accurate optical models include SOCS kernels that provide successively less influence. Corresponding resist models are constructed that may include only SOCS kernel terms corresponding to the optical model, or may include image trait terms of varying influence ranges. Errors associated with excessive light, such as bridging, side- lobe or SRAF printing errors, are preferably identified with bright field simulations, while errors associated with insufficient light, such as necking or line-end shortening overlay errors, are preferably identified with dark field simulations.

Abstract translation: 提供了一种验证光刻掩模设计的快速方法，其中通过使用逐渐更准确的图像模型（411）迭代地模拟和验证用于掩模布局的图像来识别灾难性错误（432），包括光学和抗蚀剂模型。 逐步精确的光学模型包括提供连续影响较小的SOCS内核。 构造相应的抗蚀剂模型，其可以仅包括对应于光学模型的SOCS核项，或者可以包括不同影响范围的图像特征项。 优选地通过明亮的场模拟来识别与过度的光相关的错误，例如桥接，旁瓣或SRAF打印错误，而与不充分的光相关的错误，例如颈缩或线端缩短覆盖误差，优选地用暗场 模拟。

公开(公告)号：WO2011116127A1

公开(公告)日：2011-09-22

申请号：PCT/US2011/028720

申请日：2011-03-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BAGHERI, Saeed ,  INOUE, Tadanobu ,  MELVILLE, David O. ,  MUTA, Hidemasa ,  ROSENBLUTH, Alan E. ,  SAKAMOTO, Masahura ,  TIAN, Kehan

Inventor： BAGHERI, Saeed ,  INOUE, Tadanobu ,  MELVILLE, David O. ,  MUTA, Hidemasa ,  ROSENBLUTH, Alan E. ,  SAKAMOTO, Masahura ,  TIAN, Kehan

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F1/36 ,  G03F1/70 ,  G03F7/705

Abstract: Optical wave data for a semiconductor device design is divided into regions (102). First wavefront engineering is performed on the wave data of each region, accounting for just the wave data of each region. The optical wave date of each region is normalized based on the first wavefront engineering (106). Second wavefront engineering is performed on the wave data of each region, based at least on the wave data of each region as normalized (108). The second wavefront engineering takes into account the wave data of each region and a guard band around each region including the wave data of the neighboring regions of each region. The second wavefront engineering can be sequentially performed in parallel by organizing the regions into groups (110).

Abstract translation: 用于半导体器件设计的光波数据被划分为区域（102）。 对每个区域的波形数据执行第一波前工程，仅考虑每个区域的波形数据。 基于第一波前工程（106）对每个区域的光波日期进行归一化。 至少基于每个区域的波形数据进行归一化，对每个区域的波形数据执行第二波前工程（108）。 第二波前工程考虑了每个区域的波数据和围绕每个区域的保护带，包括每个区域的相邻区域的波数据。 可以通过将区域组织成组（110）来并行地顺序地执行第二波前工程。

公开(公告)号：WO2009131827A2

公开(公告)日：2009-10-29

申请号：PCT/US2009039703

申请日：2009-04-07

Applicant: IBM ,  STOBERT IAN P ,  ROSENBLUTH ALAN E

Inventor： STOBERT IAN P ,  ROSENBLUTH ALAN E

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.

Abstract translation: 提供了一种用于在分层集成电路布局上执行数据校正的解决方案。 一种方法包括：在数据校正之前接收用于长距离临界尺寸变化的CD补偿图; 将CD补偿的补偿量分组为多个补偿范围; 产生对应于多个补偿范围的多个目标层; 超级CD补偿图的区域具有落在相应目标层上的补偿范围内的补偿量以产生目标形状; 在布局上执行数据校正以生成数据校正布局; 分别对目标形状进行数据校正，生成数据校正对象的形状; 并且基于CD补偿图组合数据校正布局和数据校正目标形状。

公开(公告)号：WO2012009183A3

公开(公告)日：2012-04-26

申请号：PCT/US2011042991

申请日：2011-07-06

Applicant: IBM ,  BAGHERI SAEED ,  DEMARIS DAVID L ,  GABRANI MARIA ,  MELVILLE DAVID OSMOND ,  ROSENBLUTH ALAN E ,  TIAN KEHAN

Inventor： BAGHERI SAEED ,  DEMARIS DAVID L ,  GABRANI MARIA ,  MELVILLE DAVID OSMOND ,  ROSENBLUTH ALAN E ,  TIAN KEHAN

IPC: H01L21/027 ,  H01L21/66

CPC classification number: G03F1/70 ,  G06F17/5081

Abstract: The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate i{ of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate ft, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate 6,, and a total energy entropy factor comprising total energy entropy of said diffraction orders (430, 440). The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=l, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=l. The value of the lithographic difficulty metric may be used to identify patterns in a design layout that are binding patterns in an optimization computation. The lithographic difficulty metric may be used to design integrated circuits that have good, relatively easy-to-print characteristics.

Abstract translation: 本发明提供了一种光刻难度度量，其是能量比因子的函数，能量比因子包括沿着沿着空间频率空间的角坐标i的衍射级的难以打印能量的容易打印能量的比率， 包括沿着所述角坐标ft的所述衍射级的能量熵的能量熵因子，包括沿着所述角坐标6的所述衍射级的相位熵的相位熵因子，以及包括所述衍射级的总能量熵的总能量熵因子 430,440）。 难以打印的能量包括在r = 0和r = 1附近的空间频率空间的归一化径向坐标r的值的衍射级的能量，并且易于打印的能量包括 位于r = 0附近和r = 1附近的归一化径向坐标r的中间值处的衍射级的能量。 光刻难度度量的值可用于识别在优化计算中的结合模式的设计布局中的图案。 光刻难度度可用于设计具有良好的，相对易于打印的特性的集成电路。

公开(公告)号：WO2010080796A1

公开(公告)日：2010-07-15

申请号：PCT/US2010/020209

申请日：2010-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  AZPIROZ, Jaione, Tirapu ,  ROSENBLUTH, Alan, E. ,  GRAUR, Ioana, C.

Inventor： AZPIROZ, Jaione, Tirapu ,  ROSENBLUTH, Alan, E. ,  GRAUR, Ioana, C.

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/705

Abstract: The present invention relates to the modeling of lithographic processes for use in the design of photomasks for the manufacture of semiconductor integrated circuits, and particularly to the modeling of the complex effects due to interaction of the illuminating light with the mask topography. According to the invention, an isofield perturbation to a thin mask representation of the mask is provided by determining, for the components of the illumination, differences between the electric field on a feature edge having finite thickness and on the corresponding feature edge of a thin mask representation. An isofield perturbation is obtained from a weighted coherent combination of the differences for each illumination polarization. The electric field of a mask having topographic edges is represented by combining a thin mask representation with the isofield perturbation applied to each edge of the mask.

Abstract translation: 本发明涉及用于制造半导体集成电路的光掩模的设计中使用的光刻工艺的建模，特别涉及由于照明光与掩模形貌的相互作用引起的复杂效应的建模。 根据本发明，通过确定对于照明的组件，具有有限厚度的特征边缘上的电场与薄掩模的相应特征边缘之间的差异来确定对掩模的薄掩模表示的异场扰动 表示。 从每个照明偏振的差异的加权相干组合获得异场扰动。 通过将薄掩模表示与施加到掩模的每个边缘的异场扰动组合来表示具有形貌边缘的掩模的电场。

公开(公告)号：WO2009131827A3

公开(公告)日：2009-10-29

申请号：PCT/US2009/039703

申请日：2009-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STOBERT, Ian, P. ,  ROSENBLUTH, Alan, E.

Inventor： STOBERT, Ian, P. ,  ROSENBLUTH, Alan, E.

IPC: G06F17/50

Abstract: A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.

公开(公告)号：WO2009091784A1

公开(公告)日：2009-07-23

申请号：PCT/US2009/030934

申请日：2009-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LAVIN, Mark, A. ,  MUKHERJEE, Maharaj ,  ROSENBLUTH, Alan, E.

Inventor： LAVIN, Mark, A. ,  MUKHERJEE, Maharaj ,  ROSENBLUTH, Alan, E.

IPC: G06F17/50

CPC classification number: G03F7/705 ,  G03F1/36

Abstract: A method, system and computer program product for rendering a mask are disclosed. A method of rendering a mask may comprise: providing an initial mask design for a photolithographic process, the initial mask design including polygons; initially rendering the initial mask design as a coarse mask representation in a pixel based image calculation; identifying an overhang portion; and rendering the overhang portion using a set of subpixels whose artifacts from spatial-localization lie outside a practical resolution of a pseudo lens having a numerical aperture larger than that of a projection lens used in the photolithographic process; and updating the initial rendering based on the overhang portion rendering.

Abstract translation: 公开了一种用于渲染掩模的方法，系统和计算机程序产品。 渲染掩模的方法可以包括：提供用于光刻工艺的初始掩模设计，初始掩模设计包括多边形; 最初在基于像素的图像计算中将初始掩模设计呈现为粗糙掩模表示; 识别突出部分; 以及使用一组子空间渲染悬伸部分，其子空间的伪影位于具有大于在光刻工艺中使用的投影透镜的数值孔径的伪透镜的实际分辨率之外; 并基于突出部分呈现来更新初始呈现。

公开(公告)号：WO2008057996A3

公开(公告)日：2008-07-10

申请号：PCT/US2007083441

申请日：2007-11-02

Applicant: IBM ,  LAI KAFAI ,  ROSENBLUTH ALAN E ,  GALLATIN GREGG M ,  MUKHERJEE MAHARAJ

Inventor： LAI KAFAI ,  ROSENBLUTH ALAN E ,  GALLATIN GREGG M ,  MUKHERJEE MAHARAJ

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A fast method of verifying a lithographic mask design is provided wherein catastrophic errors (432) are identified by iteratively simulating and verifying images for the mask layout using progressively more accurate image models (411), including optical and resist models. Progressively accurate optical models include SOCS kernels that provide successively less influence. Corresponding resist models are constructed that may include only SOCS kernel terms corresponding to the optical model, or may include image trait terms of varying influence ranges. Errors associated with excessive light, such as bridging, side- lobe or SRAF printing errors, are preferably identified with bright field simulations, while errors associated with insufficient light, such as necking or line-end shortening overlay errors, are preferably identified with dark field simulations.

Abstract translation: 提供了验证光刻掩模设计的快速方法，其中通过使用包括光学和抗蚀剂模型的逐渐更准确的图像模型（411）迭代模拟和验证掩模布局的图像来识别灾难性错误（432）。 逐渐精确的光学模型包括提供连续影响较小的SOCS内核。 构建对应的抗蚀剂模型，其可以仅包括对应于光学模型的SOCS内核项，或者可以包括不同影响范围的图像特征项。 与过量光相关的错误，例如桥接，旁瓣或SRAF打印错误，优选地用明场模拟来识别，而与光线不足有关的错误例如颈缩或线端缩短覆盖错误优选地用暗场识别 模拟。