DATA CORRECTING HIERARCHICAL INTEGRATED CIRCUIT LAYOUT ACCOMMODATING COMPENSATE FOR LONG RANGE CRITICAL DIMENSION VARIATION
    1.
    发明申请
    DATA CORRECTING HIERARCHICAL INTEGRATED CIRCUIT LAYOUT ACCOMMODATING COMPENSATE FOR LONG RANGE CRITICAL DIMENSION VARIATION 审中-公开
    数据校正分层整合电路布局扩展补偿长期关键尺寸变化

    公开(公告)号:WO2009131827A2

    公开(公告)日:2009-10-29

    申请号:PCT/US2009039703

    申请日:2009-04-07

    CPC classification number: G06F17/5081 G03F1/36

    Abstract: A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.

    Abstract translation: 提供了一种用于在分层集成电路布局上执行数据校正的解决方案。 一种方法包括:在数据校正之前接收用于长距离临界尺寸变化的CD补偿图; 将CD补偿的补偿量分组为多个补偿范围; 产生对应于多个补偿范围的多个目标层; 超级CD补偿图的区域具有落在相应目标层上的补偿范围内的补偿量以产生目标形状; 在布局上执行数据校正以生成数据校正布局; 分别对目标形状进行数据校正,生成数据校正对象的形状; 并且基于CD补偿图组合数据校正布局和数据校正目标形状。

    METHOD FOR FAST ESTIMATION OF LITHOGRAPHIC BINDING PATTERNS IN AN INTEGRATED CIRCUIT LAYOUT
    2.
    发明申请
    METHOD FOR FAST ESTIMATION OF LITHOGRAPHIC BINDING PATTERNS IN AN INTEGRATED CIRCUIT LAYOUT 审中-公开
    用于快速估计集成电路布局中的平面结合图案的方法

    公开(公告)号:WO2012009183A3

    公开(公告)日:2012-04-26

    申请号:PCT/US2011042991

    申请日:2011-07-06

    CPC classification number: G03F1/70 G06F17/5081

    Abstract: The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate i{ of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate ft, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate 6,, and a total energy entropy factor comprising total energy entropy of said diffraction orders (430, 440). The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=l, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=l. The value of the lithographic difficulty metric may be used to identify patterns in a design layout that are binding patterns in an optimization computation. The lithographic difficulty metric may be used to design integrated circuits that have good, relatively easy-to-print characteristics.

    Abstract translation: 本发明提供了一种光刻难度度量,其是能量比因子的函数,能量比因子包括沿着沿着空间频率空间的角坐标i的衍射级的难以打印能量的容易打印能量的比率, 包括沿着所述角坐标ft的所述衍射级的能量熵的能量熵因子,包括沿着所述角坐标6的所述衍射级的相位熵的相位熵因子,以及包括所述衍射级的总能量熵的总能量熵因子 430,440)。 难以打印的能量包括在r = 0和r = 1附近的空间频率空间的归一化径向坐标r的值的衍射级的能量,并且易于打印的能量包括 位于r = 0附近和r = 1附近的归一化径向坐标r的中间值处的衍射级的能量。 光刻难度度量的值可用于识别在优化计算中的结合模式的设计布局中的图案。 光刻难度度可用于设计具有良好的,相对易于打印的特性的集成电路。

    PRINTABILITY VERIFICATION BY PROGRESSIVE MODELING ACCURACY
    3.
    发明申请
    PRINTABILITY VERIFICATION BY PROGRESSIVE MODELING ACCURACY 审中-公开
    通过逐步建模准确性进行可打印性验证

    公开(公告)号:WO2008057996A3

    公开(公告)日:2008-07-10

    申请号:PCT/US2007083441

    申请日:2007-11-02

    CPC classification number: G03F1/36

    Abstract: A fast method of verifying a lithographic mask design is provided wherein catastrophic errors (432) are identified by iteratively simulating and verifying images for the mask layout using progressively more accurate image models (411), including optical and resist models. Progressively accurate optical models include SOCS kernels that provide successively less influence. Corresponding resist models are constructed that may include only SOCS kernel terms corresponding to the optical model, or may include image trait terms of varying influence ranges. Errors associated with excessive light, such as bridging, side- lobe or SRAF printing errors, are preferably identified with bright field simulations, while errors associated with insufficient light, such as necking or line-end shortening overlay errors, are preferably identified with dark field simulations.

    Abstract translation: 提供了验证光刻掩模设计的快速方法,其中通过使用包括光学和抗蚀剂模型的逐渐更准确的图像模型(411)迭代模拟和验证掩模布局的图像来识别灾难性错误(432)。 逐渐精确的光学模型包括提供连续影响较小的SOCS内核。 构建对应的抗蚀剂模型,其可以仅包括对应于光学模型的SOCS内核项,或者可以包括不同影响范围的图像特征项。 与过量光相关的错误,例如桥接,旁瓣或SRAF打印错误,优选地用明场模拟来识别,而与光线不足有关的错误例如颈缩或线端缩短覆盖错误优选地用暗场识别 模拟。

    IMPROVING THE STABILITY OF ION BEAM GENERATED ALIGNMENT LAYERS BY SURFACE MODIFICATION
    5.
    发明申请
    IMPROVING THE STABILITY OF ION BEAM GENERATED ALIGNMENT LAYERS BY SURFACE MODIFICATION 审中-公开
    通过表面改性改善离子束生成对准层的稳定性

    公开(公告)号:WO02057839A3

    公开(公告)日:2003-03-13

    申请号:PCT/US0144989

    申请日:2001-11-30

    Applicant: IBM

    CPC classification number: G02F1/13378

    Abstract: A method for preparing a alignment layer surface provides a surface on the alignment layer. A chemically modified surfae [117] is formed as a result of quenching and/or ion beam treatment in accordance with the present invention, and reactive gas is introduced to the ion beam to saturate dangling bonds on the surface. Layer [117] is now substantially free from dangling bonds and free radicals which could degrade properties of a liquid crystal display. Now, a substrate [101] is formed for use in a liquid crystal displax device. Another method for preparing an alignment layer. The surface is bombarded with ions and quenched with a reactive component to saturate dangling bonds on the surface.

    Abstract translation: 制备取向层表面的方法提供了取向层上的表面。 作为根据本发明的淬火和/或离子束处理的结果形成化学改性的表面[117],并且将反应性气体引入到离子束中以饱和表面上的悬挂键。 层[117]现在基本上没有可能劣化液晶显示器性质的悬挂键和自由基。 现在,形成用于液晶置换装置的基板[101]。 制备取向层的另一种方法。 表面用离子轰击并用反应性组分淬火以使表面上的悬挂键饱和。

    Extending range of lithographic simulation integral
    6.
    发明专利
    Extending range of lithographic simulation integral 有权
    扩展的平面模拟集成范围

    公开(公告)号:JP2005128557A

    公开(公告)日:2005-05-19

    申请号:JP2004310633

    申请日:2004-10-26

    CPC classification number: G03F1/36 G03F1/70

    Abstract: PROBLEM TO BE SOLVED: To provide a method for calculating intermediate-range and long-range image contributions from mask polygons.
    SOLUTION: An algorithm is introduced having application to optical proximity correction in optical lithography. A finite integral for each sector of a polygon replaces an infinite integral. A finite integral is achieved by integrating over two triangles instead of integrating on full sectors. An analytical approach is presented for a power law kernel to reduce the numerical integration of a sector to an analytical expression evaluation. The mask polygon is divided into a plurality of regions to calculate effects of interaction such as intermediate-range and long-range effects, by truncating the mask instead of truncating the kernel function.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题:提供一种用于从掩模多边形计算中间范围和远程图像贡献的方法。 解决方案:引入了一种应用于光学光刻中的光学邻近校正的算法。 多边形的每个扇区的有限积分代替无限积分。 通过对两个三角形进行积分而不是整个扇区进行积分来实现有限积分。 针对幂律内核提出了一种分析方法,以减少一个部门与分析表达式评估的数值整合。 掩模多边形被划分成多个区域,以通过截断掩码而不是截断核函数来计算诸如中间范围和长距离效应的交互的效果。 版权所有(C)2005,JPO&NCIPI

    REFLECTION-TYPE LIGHT BULB AND PROJECTING DEVICE

    公开(公告)号:JP2000258764A

    公开(公告)日:2000-09-22

    申请号:JP2000052801

    申请日:2000-02-29

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To obtain a light bulb containing a twisted nematic liquid crystal(LC) layer in which the contrast and efficiency are improved and visibility of spacer posts in a black state is decreased by forming a reflection electrode with its edges parallel or perpendicular to the director axis of liquid crystal molecules when the director axis is projected on the surface of a back face. SOLUTION: A reflection pixel electrode 10 is formed on the lower side of a LC layer 4. The general alignment of the LC molecules is shown as a series of arrows from an arrow 2 on the upper face of the LC layer 4 to the arrow 3 on the lower face. The twisting orientation of the arrows from the upper part to the lower part represents the twist of the LC. The axis of the LC molecule and the rubbing direction on the lower substrate 6 are aligned along the edge of the pixel electrode 10 except for a small pretilt angle of the molecules on the back face. The polarization direction of the input polarized light is parallel or perpendicular to the LC director projected on the upper substrate. The LC director having specified depth in the LC is slightly tilted from the back face, which means that the LC director is oriented in the direction in which the refractive index for abnormal rays is minimum or maximum.

    Method for computing manufacturability of lithographic mask by selecting target edge pair
    10.
    发明专利
    Method for computing manufacturability of lithographic mask by selecting target edge pair 有权
    通过选择目标边缘对计算掩模的可制造性的方法

    公开(公告)号:JP2010140020A

    公开(公告)日:2010-06-24

    申请号:JP2009256152

    申请日:2009-11-09

    CPC classification number: G03F1/68 G03F1/78

    Abstract: PROBLEM TO BE SOLVED: To provide a method for computing manufacturability of a lithographic mask to be used for fabricating a semiconductor device. SOLUTION: A set of a plurality of target edges is selected from mask layout data of a lithographic mask (402). Then, target edge pairs are selected from the selected set of target edges (404). The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is computed based on the target edge pairs selected (406). The manufacturability of the lithographic mask is output (408). The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种用于计算用于制造半导体器件的光刻掩模的可制造性的方法。 解决方案:从光刻掩模(402)的掩模布局数据中选择一组多个目标边缘。 然后,从所选择的一组目标边缘中选择目标边缘对(404)。 基于所选择的目标边缘对(406)计算光刻掩模的可制造性,包括制造光刻掩模的制造损失。 输出光刻掩模的可制造性(408)。 光刻掩模的可制造性取决于制造光刻掩模的制造损失。 版权所有(C)2010,JPO&INPIT

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