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    AMPLIFICATEUR RADIOFRÉQUENCE
    2.
    发明申请
    AMPLIFICATEUR RADIOFRÉQUENCE 审中-公开

    公开(公告)号：WO2021165213A1

    公开(公告)日：2021-08-26

    申请号：PCT/EP2021/053678

    申请日：2021-02-15

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： LEMOINE, Renaud ,  OUYAHIA, Samia ,  WILHELM, Eric ,  BOYAVALLE, Christophe

    IPC: H03F1/02

    Abstract: Selon un aspect, il est proposé un circuit intégré comprenant un amplificateur radiofréquence comportant: - au moins deux étages amplificateurs (DS, PS), - un dispositif d'adaptation d'impédance (DAI) entre deux étages amplificateurs (DS, PS) de l'amplificateur radiofréquence, le dispositif d'adaptation comprenant deux lignes (L1, L2) couplées par induction électromagnétique, une première ligne (L1) étant reliée à une sortie du premier étage amplificateur (DS) et une deuxième ligne (L2) étant reliée à une entrée du deuxième étage amplificateur (PS).

    AMPLIFICATEUR DE PUISSANCE RADIOFREQUENCE
    3.
    发明申请
    AMPLIFICATEUR DE PUISSANCE RADIOFREQUENCE 审中-公开

    公开(公告)号：WO2021165212A1

    公开(公告)日：2021-08-26

    申请号：PCT/EP2021/053677

    申请日：2021-02-15

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： GUEGNAUD, Hervé ,  VENEC, Stéphanie ,  BLAMON, Guillaume

    IPC: H03F1/52 ,  H03F1/34 ,  H03F3/19 ,  H03G3/30 ,  H03F3/24

    Abstract: Selon un aspect, il est proposé un circuit intégré comprenant un amplificateur de puissance comportant : • une succession d'au moins deux étages amplificateurs (DS, PS) comportant un premier étage amplificateur (DS) configuré pour recevoir en entrée un signal radiofréquence et un dernier étage amplificateur (PS) configuré pour délivrer en sortie un signal radiofréquence amplifié, • un circuit de sûreté comprenant : • des moyens de contrôle (CM) configurés pour comparer une tension du signal radiofréquence amplifié (RFAMP) à une tension seuil (VTH), • des moyens de réduction (GRM) de gain configurés pour réduire une tension de polarisation d'un étage amplificateur en amont (DS) du dernier étage (PS) lorsque la tension du signal radiofréquence amplifié (RFAMP) est supérieure à la tension seuil (VTH).

    METHOD AND TRANSMITTER CIRCUIT FOR COMMUNICATION USING ACTIVE LOAD MODULATION IN RADIO FREQUENCY IDENTIFICATION SYSTEMS
    5.
    发明申请
    METHOD AND TRANSMITTER CIRCUIT FOR COMMUNICATION USING ACTIVE LOAD MODULATION IN RADIO FREQUENCY IDENTIFICATION SYSTEMS 审中-公开
    在无线电频率识别系统中使用主动负载调制的通信方法和发射机电路

    公开(公告)号：WO2017050818A1

    公开(公告)日：2017-03-30

    申请号：PCT/EP2016/072410

    申请日：2016-09-21

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： KOVACIC, Kosta ,  PEVEC, Albin

    IPC: H04B5/00

    CPC classification number: H04B5/0062 ,  H04B5/0031

    Abstract: Method and transmitter circuit for communication using active load modulation in Radio Frequency Identification systems In one embodiment a method for communication using active load modulation in Radio Frequency Identification, RFID, systems comprising the following steps of receiving a carrier signal (Sc) having a carrier frequency from a reader device, generating a modulated signal (Smod), transmitting a burst of a sending signal (Sout), and decaying the sending signal (Sout) at the end of the burst. Furthermore, atransmitter circuit (T) for communication using active load modulation in RFID systems comprising an equipment (E1, E2, E3) for generating a decaying sending signal (Sout) is specified.

    Abstract translation: 在射频识别系统中使用有源负载调制进行通信的方法和发射机电路在一个实施例中，一种在射频识别（RFID）系统中使用有源负载调制的通信方法，包括以下步骤：接收具有载波频率的载波信号 从读取器装置产生调制信号（Smod），发送发送信号（Sout）的脉冲串，并在脉冲串结束时衰减发送信号（Sout）。 此外，规定了用于在包括用于产生衰减发送信号（Sout）的设备（E1，E2，E3）的RFID系统中使用有源负载调制的通信的发送器电路（T）。

    CLOCK SIGNAL DETECTION CIRCUIT, CORRESPONDING ELECTRONIC DEVICE AND METHOD OF OPERATION
    8.
    发明申请
    CLOCK SIGNAL DETECTION CIRCUIT, CORRESPONDING ELECTRONIC DEVICE AND METHOD OF OPERATION 有权

    公开(公告)号：US20250158617A1

    公开(公告)日：2025-05-15

    申请号：US18938809

    申请日：2024-11-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Dorde CVEJANOVIC

    IPC: H03K19/17736 ,  H03K19/0185 ,  H03K19/20

    Abstract: A clock signal detection circuit includes a first input that receives an always-on clock signal, and a second input that receives an activatable clock signal. A detection flip-flop circuit has a data input terminal that receives an always-high logic signal, a clock terminal that receives the always-on clock signal, a reset terminal that receives a reset signal, and a data output terminal that produces an asynchronous clock detection signal. The reset signal is asserted to reset the detection flip-flop circuit in response to the activatable clock signal being asserted, and the reset signal is de-asserted to prevent reset of the detection flip-flop circuit in response to the activatable clock signal being de-asserted. The asynchronous clock detection signal is passed to an output to provide a clock detection signal that is asserted to indicate that the activatable clock signal is absent.

    FLIP CHIP QUAD FLAT NO LEADS (QFN) PACKAGE
    9.
    发明申请
    FLIP CHIP QUAD FLAT NO LEADS (QFN) PACKAGE 有权

    公开(公告)号：US20250157898A1

    公开(公告)日：2025-05-15

    申请号：US18389257

    申请日：2023-11-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Venero SANTAMARIA

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

    Abstract: A leadframe includes first leads and second leads, wherein each lead of the first and second leads has an upper surface. First and second silver spots are provided on the upper surface of each lead of the first and second leads. An integrated circuit die has a front surface including first and second interconnection pads. A first pillar is mounted to each first interconnection pad, and second pillar is mounted to each second interconnection pad. The integrated circuit die is mounted in flip chip orientation to the leadframe with the first pillars soldered to the first silver spots and the second pillars soldered to the second silver spots. A resin body encapsulates the integrated circuit die mounted to the leadframe.

    INTEGRATED CIRCUIT PAD WITH MULTIPLE PROBING AREAS AND METHOD OF PROBING AN INTEGRATED CIRCUIT
    10.
    发明申请
    INTEGRATED CIRCUIT PAD WITH MULTIPLE PROBING AREAS AND METHOD OF PROBING AN INTEGRATED CIRCUIT 有权

    公开(公告)号：US20250157860A1

    公开(公告)日：2025-05-15

    申请号：US18388571

    申请日：2023-11-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Alberto PAGANI ,  Mattia DE NICOLA

    IPC: H01L21/66

    Abstract: Wafer level testing is performed on a wafer including integrated circuit dies, each integrated circuit die including a die pads, with each die pad covered by a protection layer. The wafer level testing includes, at a given die pad: puncturing through the protection layer with a distal end of a probe to make physical and electrical contact with the given die pad at a first location at the given die pad; performing a first electrical test of the integrated circuit die through the probe; horizontally translating after completion of the first electrical test; puncturing through the protection layer with the distal end of the probe to make physical and electrical contact with the given die pad at a second location, different from the first location, at the given die pad; and performing a second first electrical test of the integrated circuit die through the probe.

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