Manufacturing method of wiring circuit board, wiring circuit board, and manufacturing method of multilayer wiring board
    1.
    发明专利
    Manufacturing method of wiring circuit board, wiring circuit board, and manufacturing method of multilayer wiring board 有权
    配线电路板,线路板制造方法及多层布线板制造方法

    公开(公告)号:JP2009088572A

    公开(公告)日:2009-04-23

    申请号:JP2009014166

    申请日:2009-01-26

    Inventor: KATO TAKASHI

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring circuit board capable of forming an insulating film, without exposing it to an etchant. SOLUTION: As shown in Fig.1(a), a multilayer metal plate is prepared, in which a wiring film forming metal layer 102 is formed on a releasable sheet 100, and a bump forming metal layer 104 is formed on the wiring film forming metal layer through an etching stopper layer 103. As shown in Fig.1(d), by etching the bump forming metal layer 104, bumps 107 are formed. As shown in Fig.1(f), resist 109 is applied on the surface of the bump forming layer 104 on which the bumps 107 are formed, and as shown in Fig.1(g), a resist 110 is formed by means of an exposure/development process. As shown in Fig.1(h), by etching the etching stopper layer 103 using the resist 110 as a mask, a wiring film 111 is formed. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种制造能够形成绝缘膜的布线电路板的方法,而不将其暴露于蚀刻剂。 解决方案:如图1(a)所示,制备多层金属板,其中在可剥离片材100上形成布线膜形成金属层102,并在其上形成凸起形成金属层104 通过蚀刻停止层103布线膜形成金属层。如图1(d)所示,通过蚀刻凸块形成金属层104,形成凸块107。 如图1(f)所示,在形成凸块107的凸点形成层104的表面上涂敷抗蚀剂109,如图1(g)所示,通过 曝光/开发过程。 如图1(h)所示,通过使用抗蚀剂110作为掩模蚀刻蚀刻停止层103,形成布线膜111。 版权所有(C)2009,JPO&INPIT

    Inter-layer connecting material
    2.
    发明专利
    Inter-layer connecting material 有权
    层间连接材料

    公开(公告)号:JP2008098656A

    公开(公告)日:2008-04-24

    申请号:JP2007297120

    申请日:2007-11-15

    Abstract: PROBLEM TO BE SOLVED: To obtain an inter-layer connecting material wherein microscopic formation vias can be formed at all interlayers.
    SOLUTION: The inter-layer connecting material includes: a metal layer that is patternable for forming a wiring circuit pattern and has a first main surface with a continuous flat shape and a second main surface with the continuous flat shape on the opposite side of the first main surface; and a second layer lying on the first main surface, wherein a removable layer comprising polymer lies on a stripping layer. Further, the patternable inter-layer connecting material includes: the removable layer wherein the second layer is peelable by means of the strippping layer, which temporarity adheres the second layer to the first metal layer and is fit so as to be peeled from the first metal layer; and a plurality of solid metal bump, which lies on the second main surface and is formed of the second metal, respectively.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:获得层间连接材料,其中可以在所有中间层上形成微观形成通孔。 解决方案:层间连接材料包括:金属层,其可图案化以形成布线电路图案,并具有连续平坦形状的第一主表面和在相对侧具有连续平坦形状的第二主表面 的第一主表面; 以及位于第一主表面上的第二层,其中包含聚合物的可移除层位于剥离层上。 此外,可图案化的层间连接材料包括:可移除层,其中第二层可以通过剥离层剥离,该时间​​性将第二层粘附到第一金属层并且被配合以便从第一金属 层; 以及分别位于第二主表面上并由第二金属形成的多个固体金属凸块。 版权所有(C)2008,JPO&INPIT

    Multilayer wiring circuit forming board, and manufacturing method therefor
    3.
    发明专利
    Multilayer wiring circuit forming board, and manufacturing method therefor 有权
    多层布线电路板及其制造方法

    公开(公告)号:JP2007329514A

    公开(公告)日:2007-12-20

    申请号:JP2007238060

    申请日:2007-09-13

    Abstract: PROBLEM TO BE SOLVED: To increase height of a bump while not blocking miniaturization of patterns. SOLUTION: A multilayer wiring circuit board: forms a bump for connecting between upper and lower wirings 6 made in one or integrally made of copper on a copper layer 5; laminates a metal plate 35 formed with extended bumps so as to electrically connect each extended bump to each bump for connecting between upper and lower wirings 6 associated with the extended bump at a position associating with each bump for connecting between upper and lower wirings 6 on an interlayer insulating film of one substrate in which an interlayer insulating film 7 is formed at a portion where there is not a bump on the copper layer 5 and an upper surface of the bump for connecting between upper and lower wirings; and forms an interlayer insulating film 39 at a portion where an extended bump 38 of a metal plate is not formed. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:增加凸块的高度,同时不阻碍图案的小型化。 解决方案:多层布线电路板:形成用于连接在铜层5上由铜制成的一体或整体制成的上布线6和下布线6之间的凸块; 层叠形成有延伸凸块的金属板35,以便将每个延伸的凸块电连接到每个凸起,用于在与每个凸起相关联的位置处的上部和下部布线6之间连接延伸的凸起,以在上部和下部布线6之间连接 在铜层5上没有凸点的部分形成层间绝缘膜7的一个基板的层间绝缘膜和用于连接上下布线的凸块的上表面; 并且在未形成金属板的延伸凸块38的部分形成层间绝缘膜39。 版权所有(C)2008,JPO&INPIT

    Method of forming bump structure and the bump structure
    4.
    发明专利
    Method of forming bump structure and the bump structure 审中-公开
    形成BUK结构和BUMP结构的方法

    公开(公告)号:JP2009123863A

    公开(公告)日:2009-06-04

    申请号:JP2007295299

    申请日:2007-11-14

    Inventor: ENDO KIMIYOSHI

    Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a bump structure capable of actualizing a bump with a high aspect ratio and achieving little variation of height in a plurality of bumps when formed and a fine pitch between the bumps, and the bump structure. SOLUTION: The method of forming the bump structure includes, to attain the purpose, a step of forming a through-hole 2 in the thickness direction of a bump-forming die body 1 constituted of a plate-like metallic member, a step of forming a bump-forming recess 4 by overlapping a bump-forming die lid 3 constituted of a plate-like metallic member on the bump-forming die body 1 to cover one of openings of the through-hole 2, a step of forming a metallic layer 6 at least inside the recess 4, and a step of forming the bump structure including a protrusion 7 formed of the metallic layer 6 by removing the bump-forming die body 1 and the bump-forming die lid 3 and taking out the metallic layer 6. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种形成能够实现具有高纵横比的凸块的凸块结构的方法,并且在形成时在多个凸块中实现很小的高度变化以及凸块之间的微细间距,并且 碰撞结构。 解决方案:为了达到此目的,形成凸块结构的方法包括在由板状金属构件构成的凸块形成模体1的厚度方向上形成通孔2的步骤, 通过将由凸块形成模具主体1上的板状金属构件构成的凸块形成模具盖3重叠以覆盖通孔2的开口之一来形成凸块形成凹部4的步骤, 至少在凹部4的内部的金属层6,以及通过除去凸块形成模体1和凸起形成模具盖3而形成包括由金属层6形成的突起7的突起结构的步骤, 金属层6.版权所有(C)2009,JPO&INPIT

    Electronic parts mounter and its manufacturing method
    5.
    发明专利
    Electronic parts mounter and its manufacturing method 审中-公开
    电子部件安装及其制造方法

    公开(公告)号:JP2008153682A

    公开(公告)日:2008-07-03

    申请号:JP2008014206

    申请日:2008-01-24

    Abstract: PROBLEM TO BE SOLVED: To provide an electronic parts mounter and its manufacturing method, that enhance the properties in high-frequency, quick response or the like and with high reliability, by enhancing the mounting density of electronic parts and reducing the length of wirings. SOLUTION: The mounter is provided with a first wiring portion 5a in which bumps 4 are formed upward in a portion of wiring films 2a, an electronic part 6 whose electrodes are connected to the bumps 4, a second wiring portion 5b in which the bumps 4 are formed downward in a portion of wiring films 2a, an electronic part 6 whose electrodes are connected to the downward-looking bumps 4, an electronic part 6 whose electrodes are connected to the first wiring portion 5a and the wiring films 2a so that the wiring films of the first wiring portion 5a exposes downward, and the wiring films of the second wiring portion exposes upward, and an interlayer insulating resin layer 10 sealing the second wiring portion 5b and the electronic part 6 whose electrodes are connected to the wiring films 2a. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种电子零件安装机及其制造方法,其通过提高电子部件的安装密度和减小长度来提高高频,快速响应等性能并且具有高可靠性 的布线。 解决方案:贴片机设置有第一布线部分5a,其中突起4在布线膜2a的一部分中形成为上部,电极连接到凸块4的电子部件6,第二布线部分5b 在布线膜2a的一部分中形成有凸块4,电极与向下观察的凸块4连接的电子部件6,电极与第一布线部分5a和布线膜2a连接的电子部件6 第一布线部分5a的布线膜向下露出,并且第二布线部分的布线膜向上暴露,并且密封第二布线部分5b和电极连接到布线的电子部件6的层间绝缘树脂层10 电影2a。 版权所有(C)2008,JPO&INPIT

    Manufacturing method of member for wiring circuit
    7.
    发明专利
    Manufacturing method of member for wiring circuit 有权
    配线电路的制造方法

    公开(公告)号:JP2008211256A

    公开(公告)日:2008-09-11

    申请号:JP2008147036

    申请日:2008-06-04

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a member for a wiring circuit to expose the top surface of a metallic bump 8 by polishing its surface for utilizing the metallic bump as an interlayer connecting means, after the metallic bump 8 is formed on the surface of a metal plate 2 and an insulating layer 14 is formed for an interlayer insulation to fill a space between the metallic bumps 8, 8, or to improve reliability in connection between the metallic bump 8 and a metal plate 30 connected thereto, and reliability in the insulating layer for the interlayer insulation, in the manufacturing method for the member of a wiring circuit to coat a metal film on its surface.
    SOLUTION: An insulating sheet 14 is laminated by heating and compressing on the surface at the forming side of the metallic bump on the metal plate 2, and its surface is polished so as to expose the top surface of the metallic bump 8. A film-peeling sheet 26 is then laminated on the polished surface by heating and compressing, and its surface is polished together with the film-peeling sheet 26 to expose the top surface of the metallic bump 8. Then the film-peeling sheet 26 is exfoliated.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 解决的问题:为了提供一种用于布线电路的部件的制造方法,通过抛光金属凸块8的上表面以利用金属凸块作为层间连接装置,在金属凸块8之后, 形成在金属板2的表面上,并且形成绝缘层14用于层间绝缘以填充金属凸块8,8之间的空间,或者提高金属凸块8和连接的金属板30之间的连接的可靠性 以及用于层间绝缘的绝缘层的可靠性,在用于在其表面上涂覆金属膜的布线电路的构件的制造方法中。 解决方案:通过在金属板2上的金属凸块的成形侧的表面上进行加热和压缩来层压绝缘片14,并且其表面被抛光以暴露金属凸块8的顶表面。 然后通过加热压缩将剥离剥离片材26层压在研磨面上,将其表面与剥离片26一起进行抛光,露出金属凸块8的上表面。然后,剥离膜片26为 剥离。 版权所有(C)2008,JPO&INPIT

    Wiring circuit board, and manufacturing method thereof
    8.
    发明专利
    Wiring circuit board, and manufacturing method thereof 审中-公开
    接线电路板及其制造方法

    公开(公告)号:JP2009260402A

    公开(公告)日:2009-11-05

    申请号:JP2009187292

    申请日:2009-08-12

    Abstract: PROBLEM TO BE SOLVED: To improve reliability in connection between a top surface of a metal bump of a wiring circuit board using the metal bump as an interlayer connection means and a wiring layer connected thereto, to improve an yield of the wiring circuit board, and further to improve electrical characteristics by enhancing an insulating part between wiring layers or between wiring circuit boards. SOLUTION: In the wiring circuit board, the top surface of a metal bump 28 and a wiring film 10 (16) connected thereto are connected by the direct metal bonding of metals, for example, copper-to-copper bonding. Furthermore, air or a foamed resin 12 containing air is used as an interlayer insulating film. Thus, reliability in the connection between the top surface of the metal bump and the wiring layer is improved, and the yield of the wiring circuit board can be enhanced. When interlayer insulation is implemented by using air or the foamed resin, the dielectric constant of an interlayer insulator is reduced to lower the parasitic capacitance of the wiring circuit board or an electronic circuit using the wiring board, thereby improving circuit characteristics and performance. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题:为了提高使用金属凸块作为层间连接装置的布线电路板的金属凸块的顶表面和与其连接的布线层之间的连接可靠性,以提高布线电路的产量 进一步通过增强布线层之间或布线电路板之间的绝缘部分来改善电特性。 解决方案:在布线电路板中,通过金属的直接金属接合(例如铜 - 铜)接合金属凸块28的上表面和与其连接的布线膜10(16)连接。 此外,使用含有空气的空气或发泡树脂12作为层间绝缘膜。 因此,提高了金属凸块的上表面与布线层之间的连接的可靠性,并且可以提高布线电路板的成品率。 当通过使用空气或发泡树脂实现层间绝缘时,层间绝缘体的介电常数降低,以降低布线电路板或使用布线板的电子电路的寄生电容,从而提高电路特性和性能。 版权所有(C)2010,JPO&INPIT

    Wiring circuit board
    9.
    发明专利
    Wiring circuit board 有权
    接线电路板

    公开(公告)号:JP2009111417A

    公开(公告)日:2009-05-21

    申请号:JP2009004415

    申请日:2009-01-13

    Abstract: PROBLEM TO BE SOLVED: To provide a wiring circuit board in which not only the cost for forming the means for connection between upper and lower circuit conductors can be reduced and which is adaptable to production of a wide variety of products with small volume for each, but also the production of a narrow variety of products with large volume for each, by enhancing the productivity of the wiring circuit board that possesses different circuit conductor patterns, depending on the product model.
    SOLUTION: The wiring circuit board uses a number of metal protrusions 53, 57 which penetrates an interlayer insulating film interposed between metal layers, as the means for connection between upper and lower conductors, wherein the protrusions 53, 57 for connection between upper and lower conductors are positioned at the respective crossing points of a lattice arranged at fixed intervals.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种布线电路板,其不仅可以降低用于形成上下导体之间的连接装置的成本,并且适合于生产具有小体积的各种各样的产品 根据产品型号,通过提高具有不同电路导体图案的布线电路板的生产率,为每种产品生产各种具有大容积的产品。 解决方案:布线电路板使用多个金属突起53,57,它们贯穿介于金属层之间的层间绝缘膜,作为上导体和下导体之间的连接装置,其中用于连接上部和下部导体之间的突起53,57 并且下导体位于以固定间隔布置的格子的各个交叉点处。 版权所有(C)2009,JPO&INPIT

    Wiring circuit board
    10.
    发明专利
    Wiring circuit board 审中-公开
    接线电路板

    公开(公告)号:JP2007235167A

    公开(公告)日:2007-09-13

    申请号:JP2007122786

    申请日:2007-05-07

    Abstract: PROBLEM TO BE SOLVED: To provide a wiring circuit board in which the cost for forming the means for connection between upper and lower circuit conductors can be reduced and which is adaptable to production of a wide variety of products with small volume for each as well as production of a narrow variety of products with large volume for each by enhancing the productivity of the wiring circuit board that possesses different circuit conductor patterns depending on the product.
    SOLUTION: The wiring circuit board uses a number of metal protrusions 53(57), which penetrates an interlayer insulating film interposed between metal layers, as the means for connection between upper and lower conductors, wherein the protrusions 53(57) for connection between upper and lower conductors are positioned at cross points of a lattice arranged with fixed intervals.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种布线电路板,其中可以降低用于形成用于连接上下电路导体的装置的成本,并且适用于每种产生具有小体积的各种各样的产品 以及通过根据产品提高具有不同电路导体图案的布线电路板的生产率,生产各种具有大体积的产品。 解决方案:布线电路板使用多个贯穿介于金属层之间的层间绝缘膜的金属突起53(57)作为上导体与下导体之间的连接装置,其中,突起53(57)用于 上导体和下导体之间的连接位于以固定间隔布置的格子的交叉点处。 版权所有(C)2007,JPO&INPIT

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