公开(公告)号：WO2011029185A1

公开(公告)日：2011-03-17

申请号：PCT/CA2010/001403

申请日：2010-09-09

Applicant: ATI TECHNOLOGIES ULC ,  TOPACIO, Roden R. ,  LOW, Yip Seng

Inventor： TOPACIO, Roden R. ,  LOW, Yip Seng

IPC: H01L21/60 ,  H01L23/488 ,  H05K13/04

CPC classification number: H01L23/49838 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/05624 ,  H01L2924/01039 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads.

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供一种制造方法，其包括在半导体芯片的第一侧上形成第一导体结构，并形成与第一导体结构电接触的第二导体结构。 第二导体结构适于耦合到焊料结构并且包括具有至少两个胎面的阶梯布置。

公开(公告)号：WO2008026077A3

公开(公告)日：2011-03-03

申请号：PCT/IB2007003615

申请日：2007-08-31

Applicant: ATI TECHNOLOGIES ULC ,  MCLELLAN NEIL R ,  CHAN VINCENT K ,  TOPACIO RODEN R

Inventor： MCLELLAN NEIL R ,  CHAN VINCENT K ,  TOPACIO RODEN R

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/48

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An integrated circuit package includes an encapsulant retention structure located adjacent to a die on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the die. The retention structure placed on the substrate may also serve as a substrate stiffener to maintain mechanical properties of the substrate, allowing use of a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener allows passive electronic components to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, where a larger strip with a plurality of integrated circuit packages is produced industrially and then singulated.

Abstract translation: 集成电路封装包括邻近衬底上的管芯的密封剂保留结构。 该结构允许更大量的密封剂的放置和保持在模具下渗出。 放置在衬底上的保持结构也可以用作衬底加强件，以保持衬底的机械性能，从而允许使用更理想的更薄衬底。 在一个实施例中，在加强件中使用开口和凹槽允许无源电子部件在使用更薄的衬底时保持机械性能。 使用保留壁或加强件允许使用带状矩阵来制造这些集成电路封装，其中具有多个集成电路封装的较大条带在工业上制造然后被分割。

公开(公告)号：WO2013088263A3

公开(公告)日：2013-06-20

申请号：PCT/IB2012/003096

申请日：2012-12-11

Applicant: ATI TECHNOLOGIES ULC ,  TOPACIO, Roden R. ,  MARTINEZ, Liane ,  LOW, Yip Seng

Inventor： TOPACIO, Roden R. ,  MARTINEZ, Liane ,  LOW, Yip Seng

IPC: H05K1/14 ,  H05K7/20

Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.

公开(公告)号：WO2008087530A1

公开(公告)日：2008-07-24

申请号：PCT/IB2008/000091

申请日：2008-01-15

Applicant: ATI TECHNOLOGIES ULC ,  ATI INTERNATIONAL SRL ,  TOPACIO, Roden, R. ,  CHAN, Vincent, K.

Inventor： TOPACIO, Roden, R. ,  CHAN, Vincent, K.

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3142 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01322

Abstract: An integrated circuit product includes a die and an insulation layer. The insulation layer is operatively coupled to the die. The insulation layer includes a plurality of bump apertures. The insulation layer also includes an underfill anchor structure. Methods for making such an integrated circuit product are also described.

Abstract translation: 集成电路产品包括管芯和绝缘层。 绝缘层可操作地耦合到管芯。 绝缘层包括多个凸起孔。 绝缘层还包括底部填充锚结构。 还描述了制造这种集成电路产品的方法。

公开(公告)号：WO2013088263A2

公开(公告)日：2013-06-20

申请号：PCT/IB2012003096

申请日：2012-12-11

Applicant: CANADIAN INTELLECTUAL PROPERTY OFFICEATI TECHNOLOGIES ULC ,  TOPACIO RODEN R ,  MARTINEZ LIANE ,  LOW YIP SENG

Inventor： TOPACIO RODEN R ,  MARTINEZ LIANE ,  LOW YIP SENG

IPC: H05K1/14

CPC classification number: H01L23/36 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2924/00

Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.

Abstract translation: 根据一个实施例，一种用于封装封装器件的顶部封装和底部封装之间的封装封装式散热器插入器可以包括位于顶部封装之下的顶部散热器; 在顶部散热器下方的插入器基板; 位于插入器底部下方的底部散热器; 在所述插入器基板和所述顶部散热器之间的第一内插基板金属层; 在所述插入器基板和所述底部散热器之间的第二插入件基板金属层; 以及在第二插入器基板金属层和底部封装之间的插入件焊球。

公开(公告)号：WO2012177450A1

公开(公告)日：2012-12-27

申请号：PCT/US2012/042137

申请日：2012-06-13

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC. ,  TOPACIO, Roden, R. ,  LEE, I-Tseng

Inventor： TOPACIO, Roden, R. ,  LEE, I-Tseng

IPC: H01L23/485 ,  H01L23/31 ,  H01L21/60

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05561 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a first polymer film (80) to a side of a semiconductor chip (15 )and forming a first underbump metallization structure (75) with at least a portion on the first polymer film. (80) A second polymer film (118) is applied on the first polymer film (80) with an opening (205) exposing a portion of the first underbump metallization structure (75).

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供一种制造方法，其包括将第一聚合物膜（80）施加到半导体芯片（15）的一侧，并且在第一聚合物膜上的至少一部分形成第一底部金属化结构（75） 。 （80）将第二聚合物膜（118）施加在第一聚合物膜（80）上，其中开口（205）露出第一底部金属化结构（75）的一部分。

公开(公告)号：WO2010020033A1

公开(公告)日：2010-02-25

申请号：PCT/CA2009/001086

申请日：2009-07-31

Applicant: ATI TECHNOLOGIES ULC ,  ZBRZEZNY, Adam R. ,  TOPACIO, Roden R.

Inventor： ZBRZEZNY, Adam R. ,  TOPACIO, Roden R.

IPC: H01L23/488 ,  H01L21/77 ,  H01L23/50

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/02 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H05K3/3457 ,  H05K2201/0373 ,  Y02P70/611

Abstract: An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described.

Abstract translation: 集成电路封装采用包括适于接收焊料的预定三维表面的焊盘。 在一个示例中，预定的三维表面包括至少一个预定的山丘或突出部分和在山丘部分和谷部之间具有预定相对高度的诸如下部分的谷部分。 预定的三维表面可以以任何合适的配置进行配置，并且可以包括轮廓图案，非图案或任何其它合适的配置。 还描述了相关方法。

公开(公告)号：WO2012134710A8

公开(公告)日：2012-12-06

申请号：PCT/US2012027631

申请日：2012-03-03

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES INC ,  TOPACIO RODEN R ,  SU MICHAEL Z ,  MCLELLAN NEIL

Inventor： TOPACIO RODEN R ,  SU MICHAEL Z ,  MCLELLAN NEIL

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02233 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip (15) that has a first conductor pad (85) and a passivation structure (45). A second conductor pad (120) is fabricated around but not in physical contact with the first conductor pad (85) to leave a gap (125). The second conductor pad (120) is adapted to protect a portion of the passivation structure (45).

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供了一种制造方法，其包括提供具有第一导体焊盘（85）和钝化结构（45）的半导体芯片（15）。 围绕第二导体焊盘（85）制造第二导体焊盘（120）而不与第一导体焊盘（85）物理接触以留下间隙（125）。 第二导体焊盘（120）适于保护钝化结构（45）的一部分。

公开(公告)号：WO2012134710A1

公开(公告)日：2012-10-04

申请号：PCT/US2012/027631

申请日：2012-03-03

Applicant: ATI TECHOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC. ,  TOPACIO, Roden, R. ,  SU, Michael, Z. ,  MCLELLAN, Neil

Inventor： TOPACIO, Roden, R. ,  SU, Michael, Z. ,  MCLELLAN, Neil

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02233 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip (15) that has a first conductor pad (85) and a passivation structure (45). A second conductor pad (120) is fabricated around but not in physical contact with the first conductor pad (85) to leave a gap (125). The second conductor pad (120) is adapted to protect a portion of the passivation structure (45).

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 在一个方面，提供了一种制造方法，其包括提供具有第一导体焊盘（85）和钝化结构（45）的半导体芯片（15）。 第二导体焊盘（120）制造在第一导体焊盘（85）周围但不与其物理接触，以留下间隙（125）。 第二导体焊盘（120）适于保护钝化结构（45）的一部分。

公开(公告)号：WO2013032956A3

公开(公告)日：2013-09-12

申请号：PCT/US2012052408

申请日：2012-08-25

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES INC ,  TOPACIO RODEN R ,  MCLELLAN NEIL

Inventor： TOPACIO RODEN R ,  MCLELLAN NEIL

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/115 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/06 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing semiconductor chip (15) solder bump (35, 35') and under bump metallisation (UBM) (60, 60') structures and a corresponding device are disclosed. The method includes depositing a first layer (85, 235) of a first metallic material on a semiconductor chip (15) and a second layer (190) of a second metallic material on the first layer (85, 235) of the first metallic material. The first and second layers (85, 235), (190) are reflowed to form a solder structure (35, 35') with a desired ratio of the first metallic material to the second metallic material. In this way, a solder bump of desired composition may be formed without resort to bulk plating of pre-combined solder constituents where variations in solder composition after plating can lead to higher than anticipated reflow temperatures.

Abstract translation: 公开了制造半导体芯片（15）焊料凸块（35,35'）和凸块下金属化（UBM）（60,60'）结构和相应装置的方法。 该方法包括在第一金属材料的第一层（85,235）上沉积第一金属材料的第一层（85,235）和半导体芯片（15）上的第二金属材料层（190） 。 第一和第二层（85,235），（190）被回流以形成具有所需比率的第一金属材料与第二金属材料的焊料结构（35,35'）。 以这种方式，可以形成所需组成的焊料凸块，而不需要大量电镀预组合的焊料成分，其中电镀后焊料组成的变化可导致高于预期的回流温度。