公开(公告)号：JP2003179140A

公开(公告)日：2003-06-27

申请号：JP2002358268

申请日：2002-12-10

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RYU MOSHO ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/3065 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit by a double-damascene process which exhibits a wide process flexibility and can be easily adapted in mass-production process. SOLUTION: After an etch stop layer 54 is patterned for forming an opening 72 corresponding to a pattern in a connection which is formed on the first level of a two-level connection structure, an intermetallic dielectric layer 58 is provided on it and a photoresist mask 62 is provided on it. Openings 64 and 66 of the mask 62 correspond to the wiring pattern provided on the second level of the connection structure and a dielectric layer 58 is partially exposed from them. The dielectric layer 58 is etched and the etching is advanced in such a way that an opening 68 is produced in the exposed part of the stop layer 54 from the opening 72 of the interlayer dielectric layer 52. In other words, openings for both of the wiring on the second level and the connection on the first level are demarcated by a single etching process. Further, the opening 72 of the stop layer is tapered with its upper diameter being larger than its lower diameter. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH10335456A

公开(公告)日：1998-12-18

申请号：JP14035397

申请日：1997-05-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YU SUIYO ,  RYU MOSHO ,  RO KATETSU ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit by a double Damascus process which can have a wide degree of process flexibility and can be easily applied to a mass production process. SOLUTION: An etch stop layer 54 is patterned to form an opening 72 corresponding to a pattern of connection of a 2level connection structure formed at a first level, on which an intermetallic dielectric layer 58 is provided, on which a photoresist mask 62 is provided. Openings 64 and 66 in the mask 62 partially expose the dielectric layer 58 as associated with a wiring pattern of the connection structure provided at a second level. The dielectric layer 58 is etched and advanced until an opening 68 is made in a part of a stop layer 54 of an interlayer dielectric layer 52 exposed to the opening 72. That is, the openings are defined through a single etching step for both of the second level wiring and first level connection. Next, a metal layer is formed on the structure and excess metal is removed therefrom to define a second level connection structure.