公开(公告)号：JP2002110780A

公开(公告)日：2002-04-12

申请号：JP2000286177

申请日：2000-09-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YU SUIYO ,  RO KATETSU ,  YO KOKUJI

IPC: H01L21/76

Abstract: PROBLEM TO BE SOLVED: To provide the manufacturing method of STI which hardly produces defects in silicon substrates. SOLUTION: An oxidation pad layer 102 and a mask layer 104 are formed on the silicon substrate 100, a mask 104a is formed on the mask layer in the pattern of a photoresist formed thereon, and an oxidation pad layer 102a and the substrate 100 are etched, to form a trench. A first isolation layer 112 is formed on the substrate, after an oxidation liner layer 110 has been formed in the trench to partially embed the trench. Since annealing is carried out in this stage and turning into minute structure first isolation film 112 is carried out, stresses due to the difference of a thermal expansion coefficient is opened via a trench opening part. After the trench has been completely embedded by a second isolation layer 116, planarization is carried out, to complete STI.

公开(公告)号：JP2000235981A

公开(公告)日：2000-08-29

申请号：JP3925599

申请日：1999-02-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO SHOGEN ,  GO SHUNGEN ,  RO KATETSU

IPC: H01L21/3205 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a waveform pattern for the formation of a contact or a conductive wire. SOLUTION: A substrate 200 having an opening part for forming a double waveform pattern, a waveform pattern or a mutual connection is used. A barrier layer 206 having the same shape as that of the substrate 200 is formed thereon, and then a seed layer is formed on the opening part. A metal layer 210 is selectively formed for filling the opening part. A mechanochemical polishing step is performed until the substrate 200 is exposed.

公开(公告)号：JPH10256543A

公开(公告)日：1998-09-25

申请号：JP5918697

申请日：1997-03-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RO KATETSU ,  RIN KENTEI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To form a low-resistivity silicide structure to obtain adequate silicide electrode structure by forming a conductive material layer laterally extending over both side walls of a polysilicon structure. SOLUTION: A device is produced by depositing a polysilicon structure, forming openings through a layer by the photolithography, dipping it in a dil. HF soln. to laterally etch an intermediate Si oxide layer to form undercuts, thermally growing a gate electrode layer 56, depositing polysilicon into the undercut regions by the chemical vapor deposition to form polysilicon structures 58, 60, heavily implanting ions vertically in a substrate 10 with protrusions used for a mask to self-align heavily doped regions at the protrusions, depositing a thin Ti layer by the physical evaporation, quickly heat annealing at a high enough temp. to form Ti silicide regions 74.

公开(公告)号：JP2000323561A

公开(公告)日：2000-11-24

申请号：JP12757299

申请日：1999-05-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YO KOKUJI ,  YEW TRI-RUNG ,  CHIN SHINRAI ,  RO KATETSU

IPC: H01L21/76

Abstract: PROBLEM TO BE SOLVED: To reduce stresses caused by an annealing process by forming a doped silicon dioxide layer on a silicon nitride layer to fill a trench, effecting the annealing process, and removing part of the doped silicon dioxide layer by a planarization step to expose the silicon nitride layer. SOLUTION: A doped silicon dioxide layer 110 is formed on a silicon nitride layer 104 to fill a trench 106. The layer 110 is subjected to an annealing process to be highly densified. The annealing process is performed at about 800-950 deg.C. Part of the layer 110 is removed by, e.g. chemical-mechanical polishing to expose the layer 104. The coefficient of thermal expansion and Young's modulus of the layer 110 are adjusted by adjusting the doping level. This reduces stresses caused during the annealing process, and hence reduces both leaks at contacts and at thresholds or below.

公开(公告)号：JP2000036572A

公开(公告)日：2000-02-02

申请号：JP30433098

申请日：1998-10-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIOU FU-TAI ,  RO KATETSU

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To improve the flatness of an integrated circuit by hydrogen-treating a heat resistant metal oxide deposited by using a hydrogen plasma or hot hydrogen, and altering non-electric conductivity of the treated metal oxide to electric conductivity. SOLUTION: A heat resistant metal oxide layer hydrogen-treated by using a hydrogen plasma or hot hydrogen and exposed is converted into a conductive layer. Heat resistant metal oxide layers 116b1 116b2 exposed by the hydrogen- treatment are converted into conductive layers. Meanwhile, non-exposed heat resistant metal oxide layer 116a is still retained in a state of a non-conductive layer. A second conductive layer is formed on the metal oxide layer, and then patterned. As a result an upper surface of an upper electrode 118a of a capacitor 120 and first and second contact mutual connectors 121, 122 become the same relative heights. Thus, the smoothness (flatness) of the integrated circuit can be improved.

公开(公告)号：JPH11176923A

公开(公告)日：1999-07-02

申请号：JP10136698

申请日：1998-04-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  WU JUAN-YUAN ,  RO KATETSU

IPC: H01L21/76

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a trench isolation part. SOLUTION: A first insulating layer 21 is formed on a semiconductor substrate 20 through a chemical deposition means, and a photoresist layer is formed thereon. The photoresist layer is exposed, developed, and patterned by etching into a trench demarcating mask. Then, a first insulating part 21, a pad oxide layer, and a part of the semiconductor substrate 20 are etched continuously to provide trenches 22a and 22b to the semiconductor substrate 20. The trenches 22a and 22b are set different from each other in width so as to satisfy different needs of semiconductor devices. The trench 22b is wider in width than the trench 22a. The trench demarcating mask is removed. This trench isolation eliminates plate-like recess effect on the substrate, and a semiconductor device is improved in reliability.

公开(公告)号：JP2001023923A

公开(公告)日：2001-01-26

申请号：JP19410299

申请日：1999-07-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  KO KOKUTAI ,  RO KATETSU

IPC: H01L23/52 ,  H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To prevent the increase of the contact resistance of a contact pad, even when the positional discrepancy of a node contact hole occurs, by forming in a dielectric layer an opening to expose to it a source/drain region, and by extending out on the top surface of the dielectric layer the upper portion of the contact pad. SOLUTION: A shallow-trench insulation structure 320 is formed in a substrate 300, gate structures 306 are formed on the substrate 300, source/drain regions 304 are formed in the exposed portions of the substrate 300 by the gate structures 306, and a dielectric layer 308 made of silicon oxide is formed on the substrate 300 by a chemical vapor deposition method. While a contact pad 312 is formed in an opening 310 after forming in the dielectric layer 308 the opening 310 to expose to it a portion of the source/drain region 304, the contact pad 312 is so formed that its upper portion is extended out on the flat top surface of the dielectric layer 308. For example, as the material of the contact pad 312, polysilicon is used preferably.

公开(公告)号：JP2000216240A

公开(公告)日：2000-08-04

申请号：JP983399

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  RO KATETSU

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To avoid occurrence of an overhang structure at the upper corner part of a contact/via opening, by forming a conformal adhesive/via layer at a contact/via opening formed in a dielectrics layer, and performing an RF sputtering process before forming a conductive layer. SOLUTION: In a dielectrics layer 204 formed on a substrate 200, an opening 206 which exposes a metal structure 202 is formed. In order to cover the opening 206, an adhesive/barrier layer 206 which is conformal to the substrate 200 is formed. Then to remove an overhang structure 208a formed at the upper corner part of the opening 206, an RF sputtering process is performed. In the RF sputtering process, the gas flowing into a reactive chamber is ionized with an RF power source and an ion 209 is accelerated in an electric field. Then a conductive layer 212 is formed. Thus, no overhang structure takes place at the upper corner part of the contact/via opening, with a void removed.

公开(公告)号：JP2000208607A

公开(公告)日：2000-07-28

申请号：JP460099

申请日：1999-01-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO SHOGEN ,  WU JUAN-YUAN ,  RO KATETSU

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To prevent a semiconductor device from being short-circuitted due to a microscratch. SOLUTION: This method for forming an insulating part in the shape of shallow groove on a semiconductor substrate 200 is provided with a condensation process after an insulating plug 212a is chemically/physically ground. Thus, a microscratch can be prevented from forming a deep scratch by the insulating plug 212a. Therefore, short-circuitting due to the microscratch will not occur.

公开(公告)号：JP2000174231A

公开(公告)日：2000-06-23

申请号：JP34825298

申请日：1998-12-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  KO KOKUTAI ,  RO KATETSU

IPC: H01L27/04 ,  H01L21/285 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce the manufacturing time and prevent recrystallization of amorphous Si by depositing amorphous Si by the plasma CVD to form a lower electrode. SOLUTION: Source-drain regions 120 and a silicon dioxide layer 130 are formed on a substrate 110, this layer 130 can be formed by a low pressure CVD process using tetraethoxysilane as a reactive gas, the photolithography, etc., are applied to form openings for node contacts in the silicon dioxide layer 130, the low pressure CVD is separately executed to deposit a doped Si in the openings 140, thus forming node contacts 150, and the plasma CVD is executed to deposit a doped amorphous Si layer 160a on the silicon dioxide layer 130. Since the plasma CVD is executed in an adequate low temp. condition, the amorphous Si layer 160a never be recrystallized.