公开(公告)号：WO2008026228A8

公开(公告)日：2008-07-03

申请号：PCT/IT2006000629

申请日：2006-08-28

Applicant: ST MICROELECTRONICS SRL ,  ZAMPROGNO MARCO ,  CONFALONIERI PIERANGELO ,  MINUTI ALBERTO

Inventor： ZAMPROGNO MARCO ,  CONFALONIERI PIERANGELO ,  MINUTI ALBERTO

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN") input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

Abstract translation: 一种用于从差分到单端转换的电路（1），包括：具有第一（IN +）和第二（IN“）输入的差分放大级（2）;第一（5）和不同的第二 分别与转换电路（1）的输出（OUT *）和辅助输出（AUXOUT *）可操作地耦合的差分级的充电电路（6），该电路还包括第一（7） 以及第二缓冲电路，每个功能地布置在所述输出之一和所述充电电路中的一个之间，缓冲电路被配置为最小化所述输出（OUT *，AUXOUT * ）。

公开(公告)号：WO2013034595A1

公开(公告)日：2013-03-14

申请号：PCT/EP2012/067320

申请日：2012-09-05

Applicant: ST-ERICSSON SA ,  NICOLLINI, Germano ,  ZAMPROGNO, Marco

Inventor： NICOLLINI, Germano ,  ZAMPROGNO, Marco

IPC: H03K19/003 ,  H03K19/0185 ,  H03F3/185 ,  H03F1/52 ,  H03F3/30

CPC classification number: H03K17/6871 ,  H03F1/52 ,  H03F3/185 ,  H03F3/301

Abstract: An electronic USB or similar device 101 with a CMOS audio output stage 105 for driving, in a first mode, e.g., a headset via a port commonly used also in a second mode by a digital data transmission stage 103 for digital data and supply, the audio output stage P-channel transistor MP being switchably back-gate biased by a bias circuit 107 according to the operating mode to achieve high-voltage tolerance.

Abstract translation: 具有CMOS音频输出级105的电子USB或类似设备101，用于在第一模式中，例如通过数字数据传输级103用于数字数据和供应的第二模式中通常使用的端口驱动头戴式耳机， 根据操作模式，音频输出级P沟道晶体管MP由偏置电路107可切换地逆栅偏置以实现高电压容限。

公开(公告)号：WO2012041681A1

公开(公告)日：2012-04-05

申请号：PCT/EP2011/065562

申请日：2011-09-08

Applicant: ST-ERICSSON SA ,  NICOLLINI, Germano ,  MINUTI, Alberto ,  ZAMPROGNO, Marco

Inventor： NICOLLINI, Germano ,  MINUTI, Alberto ,  ZAMPROGNO, Marco

IPC: G11C27/02 ,  H03F3/45 ,  H03M1/12 ,  H03M3/02

CPC classification number: H03M1/124 ,  G11C27/026 ,  H03F3/45475 ,  H03F3/45986 ,  H03F2203/45512 ,  H03F2203/45536

Abstract: A single-ended to differential buffer circuit is (21,22) is disclosed, adapted to couple at least an input analog signal (Vin) to a receiving circuit (24). The buffer circuit (21,22) comprises an output section (22) comprising a differential amplifier (25) having a first (31) and a second (32) input, a first (41) and a second (42) output. The buffer circuit further comprises an input section (21) comprising a first (CS1) and a second (CS2) switched capacitor, each adapted to sample said input analog signal (Vin) and having a first side (p1',p2') and a second side (p1", p2"), the first sides (ρ1', ρ2') of the first and second switched capacitors being controllably connectable / disconnectable to/from said first (41) and second (42) outputs respectively. In the buffer circuit the second sides (p1",p2") of said first (CS1) and second (CS2) switched capacitors are controllably connectable/disconnectable to/from said first (31) and second (32) inputs of the differential amplifier (25) respectively. Moreover, in the buffer circuit the second sides (p1", p2") of the first and second switched capacitors (CS1,CS2) are controllably connectable/disconnectable to/from said second output (42) and said first output (41) respectively. A method (100) for coupling at least a single-ended input analog signal (Vin) to a receiving circuit (24) with differential inputs is also disclosed.

Abstract translation: 公开了一种单端到差分缓冲电路（21,22），其适于将至少一个输入模拟信号（Vin）耦合到接收电路（24）。 缓冲电路（21,22）包括输出部分（22），其包括具有第一（31）和第二（32）输入的差分放大器（25），第一输入（41）和第二输出（42）。 缓冲电路还包括一个包括第一（CS1）和第二（CS2）开关电容器的输入部分（21），每个适于对所述输入模拟信号（Vin）进行采样，并具有第一侧（p1'，p2'）和 第二侧（p1“，p2”），第一和第二开关电容器的第一边（θ1'，φ2'）分别与所述第一（41）和第二（42）输出可控地连接/断开 。 在缓冲电路中，所述第一（CS1）和第二（CS2）开关电容器的第二侧（p1“，p2”）可控地连接到/从所述差分放大器的第一（31）和第二（32）输入端连接/断开 （25）。 此外，在缓冲电路中，第一和第二开关电容器（CS1，CS2）的第二侧（p1“，p2”）分别与所述第二输出端（42）和所述第一输出端（41）可控地连接/断开 。 还公开了用于将至少单端输入模拟信号（Vin）耦合到具有差分输入的接收电路（24）的方法（100）。

公开(公告)号：WO2008023395A8

公开(公告)日：2008-07-03

申请号：PCT/IT2006000628

申请日：2006-08-25

Applicant: ST MICROELECTRONICS SRL ,  ZAMPROGNO MARCO ,  NICOLLINI GERMANO ,  MINUTI ALBERTO

Inventor： ZAMPROGNO MARCO ,  NICOLLINI GERMANO ,  MINUTI ALBERTO

IPC: H03F3/00

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (C I ) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (C pi ). The device also comprises a charging and discharging device (SW CPIR , SW G ) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

Abstract translation: 描述了一种用于开关电容电路的集成缓冲器件（2），包括： - 缓冲器（7），其具有用于依赖于输入电压（VIN）的输出电压的输出（OUT），该输出电压可以由源 ）到缓冲设备; - 可以在第一和第二条件之间切换的电容性开关元件（C _{I ），在所述第一和第二条件下，所述第一和第二条件分别连接到源极和缓冲器以将输入电压传输到输出端; 所述组件设置有具有相关寄生容量（C pi ）的终端（N2）。 该器件还包括一个充电和放电装置（SW CPIR ，SW G ），用于在占用第二个参考电压（REFM）前对杂散电容进行预充电 条件并在占用第一条件之前预先放电杂散容量。}

公开(公告)号：WO2010057900A1

公开(公告)日：2010-05-27

申请号：PCT/EP2009/065355

申请日：2009-11-18

Applicant: ST ERICSSON SA ,  ZAMPROGNO, Marco ,  GUANZIROLI, Federico ,  NICOLLINI, Germano ,  CONFALONIERI, Pierangelo

Inventor： ZAMPROGNO, Marco ,  GUANZIROLI, Federico ,  NICOLLINI, Germano ,  CONFALONIERI, Pierangelo

IPC: H03F3/50 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03F3/505 ,  H03F2200/375 ,  H03F2200/447 ,  H03F2200/453 ,  H03F2203/5031 ,  H03M1/089 ,  H03M1/12

Abstract: An analog-to-digital conversion device (100) is described, comprising: an input stage (200) arranged to receive an input signal (V in ) and to provide an output analog signal (v in' ) as a function of the input signal (v in ); an analog-to-digital conversion block (300) arranged to receive the output analog signal (v in' ) and to provide a respective output digital signal (V out ). The input stage (200) comprises: a first voltage buffer (Bl) arranged to provide the output analog signal (v in' ) to the conversion block (300) as the translation of the input signal (v in ) of an amount equal to a translation voltage; a second voltage buffer (B2) arranged to provide a first reference signal (V rif1 ) to the conversion block (300) which is representative of the translation of a first reference voltage (V ss ) of an amount equal to the translation voltage, so that the conversion block (300) result be able to store the input signal (v in ) as the difference of the input signal (v in ) and the first reference voltage (V ss ; V cc ) regardless of the translation voltage.

Abstract translation: 描述了一种模拟 - 数字转换装置（100），包括：输入级（200），被布置为接收输入信号（Vin）并提供作为输入信号的函数的输出模拟信号（vin'） VIN）; 布置成接收输出模拟信号（vin'）并提供相应的输出数字信号（Vout）的模数转换块（300）。 输入级（200）包括：第一电压缓冲器（B1），布置成将输出模拟信号（vin'）提供给转换块（300），作为输入信号（vin）的转换量等于平移 电压; 第二电压缓冲器（B2），被布置为向所述转换块（300）提供第一参考信号（Vrif1），所述第一参考信号代表与所述平移电压相等的量的第一参考电压（Vss）的转换， 转换块（300）能够将输入信号（vin）存储为输入信号（vin）和第一参考电压（Vss; Vcc）的差值，而不管平移电压如何。

公开(公告)号：WO2008026228A1

公开(公告)日：2008-03-06

申请号：PCT/IT2006/000629

申请日：2006-08-28

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN") input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

Abstract translation: 描述了用于从差分转换为单端的电路（1），包括：具有第一（IN +）和第二（IN“）输入的差分放大器级（2） 差动级的第一（5）和不同的第二充电电路（6），其可以分别与转换电路（1）的输出（OUT *）和辅助输出（AUXOUT *）可操作地耦合。 该电路还包括第一（7）和第二（8）缓冲电路，每个功能性地布置在所述输出端之一之间和所述充电电路之一之间。 缓冲器电路被配置为使得朝着所述输出（OUT *，AUXOUT *）看到的相对阻抗之间的差异最小化。

公开(公告)号：WO2012072797A1

公开(公告)日：2012-06-07

申请号：PCT/EP2011/071625

申请日：2011-12-02

Applicant: ST-Ericsson SA ,  ZAMPROGNO, Marco ,  MINUTI, Alberto ,  NICOLLINI, Germano

Inventor： ZAMPROGNO, Marco ,  MINUTI, Alberto ,  NICOLLINI, Germano

IPC: H02J7/00 ,  H02H3/20

CPC classification number: H02H3/20 ,  H02H3/207 ,  H02J1/10 ,  H02J7/0031 ,  H02J7/345

Abstract: An apparatus (100) for protecting a circuit (200) from an input voltage comprises a switchable element (10) arranged to couple the input voltage (V IN ) to the circuit (200) in response to a first control signal (DRV1) having a first value and to decouple the input voltage (V IN ) from the circuit (200) in response to the first control signal (DRV1) having a second value. A monitor stage (20) compares a monitored voltage (V MON ) to a threshold (V TH ). A controller (30) provides the first control signal (DRV1) to the switchable element (10), the first control signal (DRV1) having the first value when the monitored voltage (V MON ) is on one side of the threshold (V TH ) and the second value when the monitored voltage (V MON ) is on the other side of the threshold (V TH ), wherein the first value is independent of the input voltage (V IN ) and the second value is equal to the input voltage (V IN ).

Abstract translation: 一种用于保护电路（200）免受输入电压的装置（100）包括可转换元件（10），其被布置成响应于第一控制信号（DRV1）将输入电压（VIN）耦合到电路（200） 并且响应于具有第二值的第一控制信号（DRV1），将输入电压（VIN）与电路（200）去耦。 监视级（20）将监测电压（VMON）与阈值（VTH）进行比较。 控制器（30）向所述可切换元件（10）提供所述第一控制信号（DRV1），所述第一控制信号（DRV1）在所述监控电压（VMON）位于所述阈值（VTH）的一侧时具有所述第一值;以及 当所述监视电压（VMON）位于所述阈值（VTH）的另一侧时，所述第二值，其中所述第一值与所述输入电压（VIN）无关，并且所述第二值等于所述输入电压（VIN）。

公开(公告)号：WO2008023395A1

公开(公告)日：2008-02-28

申请号：PCT/IT2006/000628

申请日：2006-08-25

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

IPC: H03F3/00

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (C I ) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (C pi ). The device also comprises a charging and discharging device (SW CPIR , SW G ) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

Abstract translation: 描述了一种用于开关容量电路的集成缓冲器件（2），包括： - 缓冲器（7），其具有输出电压（OUT），该输出电压取决于可由源极（1）提供的输入电压（VIN） ）到缓冲装置; - 可以分别在其连接的第一和第二状态之间切换到电源和电容缓冲器以将输入电压传送到输出端的电容性开关部件（C SUB） 所述部件设置有具有相关联的杂散能力（C P1）的端子（N2）。 该装置还包括一个充电和放电装置（SW＆lt; CPIR＆gt;，＆lt;＆gt; G＆gt;），其被配置为在占用第二个参考电压之前对参考电压（REFM）预充电杂散容量 条件，并且在摄取第一个条件之前预先排出杂散容量。

公开(公告)号：WO2003007479A1

公开(公告)日：2003-01-23

申请号：PCT/EP2002/006487

申请日：2002-06-13

Applicant: STMICROELECTRONICS S.R.L. ,  CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

Inventor： CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

IPC: H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/804

Abstract: The capacitors of a first array (10A') of sampling capacitors weighted in binary code are, connected between a first common circuit node (NB+) and an input terminal to be charged to the voltage (Vin) with respect to ground (Gnd) of a signal to be converted, and in accordance with BAR technique are then selectively connected with two differential reference terminals (Vrefp, Vrefm) .At the same time the capacitors of a second array (10B') equal to the first and all connected to a second node (NB-) are selectively connected to ground (Gnd) and the lower differential voltage terminal (Vrefm). The two nodes are connected to the respective inputs of a comparator (23"). A logic unit (17") controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator (23"). Though the converter has a single-ended input, it behaves like a converter 20 with a differential input and therefore has an excellent immunity with respect to noise. Furthermore, it does not need either additional capacitors or a particularly sensitive comparator, so that it is characterized by low consumption and high speed and occupies a very small area of the integrated circuit of which it forms part.

Abstract translation: 以二进制码加权的采样电容器的第一阵列（10A'）的电容器连接在第一公共电路节点（NB +）和要被充电到相对于地的电压（Vin）的输入端子（Gnd）之间 然后根据BAR技术选择性地连接两个差分参考端（Vrefp，Vrefm），同时将第一阵列（10B'）的电容等于第一阵列（10B'），并将其全部连接到 第二节点（NB-）选择性地连接到地（Gnd）和下差分电压端（Vrefm）。 两个节点连接到比较器（23“）的相应输入端，逻辑单元（17”）根据预定的定时程序控制两个阵列的电容器的连接，并根据 比较器（23“）虽然转换器具有单端输入，但它的作用就像具有差分输入的转换器20，因此在噪声方面具有优异的抗扰度，而且不需要额外的电容器或特别敏感的 比较器，其特征在于低功耗和高速度，占据其形成部分的集成电路的非常小的面积。