公开(公告)号：JP2014013898A

公开(公告)日：2014-01-23

申请号：JP2013143038

申请日：2013-07-08

Applicant: Ziptronix Inc ,  ジプトロニクス・インコーポレイテッド

Inventor： TONG QIN-YI ,  GAIUS GILLMAN FOUNTAIN JR ,  PAUL M ENQUIST

IPC: H01L21/02 ,  H01L21/3065 ,  B23K20/00 ,  B23K20/16 ,  B23K20/24 ,  H01L21/20 ,  H01L21/58

CPC classification number: H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for binding at low temperature or room temperature which can be applied to a flat silicon and growth oxide surface, as well as to a non-planar surface having a flattened deposit material.SOLUTION: A method includes removing a by-product of interface polymerization in order to prevent reversible reaction so as to form room temperature chemical bonding of materials such as silicon, silicon oxide and SiO. The surfaces to be bonded are polished to give them the high degree of smoothness and flatness (2). For VSE, reactive ion etching or wet etching is used in order to etch the surfaces to be bonded slightly (3). The surface roughness and flatness are not reduced, and are increased by the VSE process. The etching surfaces are rinsed with a solution like ammonium hydroxide or ammonium fluoride, and the formation of a desirable chemical species on the surfaces is thereby promoted (4).

Abstract translation: 要解决的问题：提供一种可以应用于平坦的硅和生长氧化物表面的低温或室温的结合方法，以及具有平坦的沉积材料的非平面表面。方法包括 除去界面聚合的副产物以防止可逆反应，以形成诸如硅，氧化硅和SiO的材料的室温化学键合。 抛光表面，使它们具有高度的平滑度和平整度（2）。 对于VSE，使用反应离子蚀刻或湿蚀刻以便稍微蚀刻待粘合的表面（3）。 表面粗糙度和平整度不降低，并且通过VSE工艺增加。 蚀刻表面用氢氧化铵或氟化铵等溶液冲洗，从而促进表面上所需化学物质的形成（4）。

公开(公告)号：JP2013219370A

公开(公告)日：2013-10-24

申请号：JP2013108206

申请日：2013-05-22

Applicant: Ziptronix Inc ,  ジプトロニクス・インコーポレイテッド

Inventor： TONG QIN-YI

IPC: H01L21/02 ,  B23K20/00 ,  B23K20/16 ,  B23K20/24 ,  B81C1/00 ,  H01L21/3105 ,  H01L21/58 ,  H01L21/762

CPC classification number: B32B7/04 ,  B32B2250/04 ,  B81C1/00357 ,  B81C2201/019 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L21/3105 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/08059 ,  H01L2224/29186 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T428/24355 ,  Y10T428/24942 ,  Y10T428/31504 ,  Y10T428/31678 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/05442

Abstract: PROBLEM TO BE SOLVED: To provide a bonding method of a substrate for three-dimensional device integration.SOLUTION: A bonding method includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor, or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NHspecies. This may be accomplished by exposing the bonding layer to an NHOH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

Abstract translation: 要解决的问题：提供用于三维器件集成的衬底的接合方法。解决方案：接合方法包括使用具有氟化氧化物的接合层。 可以通过暴露于含氟溶液，蒸汽或气体或通过注入将氟引入粘合层。 接合层也可以使用在其形成期间将氟引入层中的方法形成。 结合层的表面用所需的物质（优选NH体系）终止。 这可以通过将结合层暴露于NHOH溶液来实现。 在室温下获得高粘结强度。 该方法还可以包括将两个结合层结合在一起并产生在接合层之间的界面附近具有峰的氟分布。 结合层之一可以包括彼此形成的两个氧化物层。 氟浓度也可以在两个氧化物层之间的界面处具有第二峰。

公开(公告)号：JP2014123722A

公开(公告)日：2014-07-03

申请号：JP2013246782

申请日：2013-11-28

Applicant: Ziptronix Inc ,  ジプトロニクス・インコーポレイテッド

Inventor： PAUL M ENGQUIST ,  GAIUS GILLMAN FOUNTAIN JR ,  TONG QIN-YI

IPC: H01L25/065 ,  H01L21/60 ,  H01L25/07 ,  H01L25/18 ,  H01L27/00

CPC classification number: H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

Abstract: PROBLEM TO BE SOLVED: To provide a three-dimensional integrated circuit device using direct wafer bonding and a method of manufacture thereof.SOLUTION: Either or both of a die 14 and a wafer 10 have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. The first and second contact structures can be exposed at bonding and electrically interconnected as a result of bonding. A via is etched and filled after bonding to expose and form an electrical interconnect to the interconnected first and second contact structures and provide electrical access to the electrical interconnect from a surface. Alternatively, the first and second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect the first and second contact structures and provide electrical access to the interconnected first and second contact structures.

Abstract translation: 要解决的问题：提供使用直接晶片接合的三维集成电路器件及其制造方法。解决方案：管芯14和晶片10中的任一个或两者具有形成在其中的半导体器件。 具有第一接触结构的第一元件被结合到具有第二接触结构的第二元件。 第一和第二接触结构可以在结合时暴露，并且由于接合而电连接。 在接合之后蚀刻并填充通孔以暴露并形成到互连的第一和第二接触结构的电互连，并提供从表面到电互连的电接入。 或者，第一接触结构和第二接触结构在接合时不暴露，并且在接合之后蚀刻和填充通孔以使第一和第二接触结构电互连，并提供对互连的第一和第二接触结构的电接触。

公开(公告)号：JP2012212885A

公开(公告)日：2012-11-01

申请号：JP2012107053

申请日：2012-05-08

Applicant: Ziptronix Inc ,  ジプトロニクス・インコーポレイテッド

Inventor： TONG QIN-YI ,  GAIUS GILLMAN FOUNTAIN JR ,  PAUL M ENQUIST

IPC: H01L21/02 ,  H01L21/3065 ,  B23K20/00 ,  H01L21/20 ,  H01L21/58

CPC classification number: H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a bonding method at low temperature or room temperature which includes cleaning and activation of a surface by cleaning or etching.SOLUTION: The method includes a step for removing byproducts of interface polymerization in order to prevent reversible reaction so that room temperature chemical bonding of silicon, silicon oxides and such a material as SiO is carried out. The surface to be bonded is polished to have appropriate smoothness and planarity (2). In the VSE, reactive ion etching or wet etching is used in order to etch the surface to be bonded slightly (3). Surface roughness and planarity do not decrease but are increased by the VSE process. The etching surface is rinsed with a solution of ammonium hydroxide or ammonium fluoride, so as to accelerate formation of a desired bonding chemical species on the surface (4).

Abstract translation: 要解决的问题：提供在低温或室温下的粘合方法，其包括通过清洁或蚀刻来清洁和激活表面。 解决方案：该方法包括用于除去界面聚合的副产物以防止可逆反应的步骤，以便进行硅，氧化硅和诸如SiO的材料的室温化学键合。 待粘合的表面被抛光以具有适当的平滑度和平面度（2）。 在VSE中，使用反应离子蚀刻或湿蚀刻以便稍微蚀刻待粘合的表面（3）。 表面粗糙度和平面度不降低，但通过VSE工艺增加。 蚀刻表面用氢氧化铵或氟化铵溶液冲洗，以便加速在表面（4）上形成所需的键合化学物质。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013058781A

公开(公告)日：2013-03-28

申请号：JP2012246660

申请日：2012-11-08

Applicant: Ziptronix Inc ,  ジプトロニクス・インコーポレイテッド

Inventor： PAUL M ENGQUIST ,  GAIUS GILLMAN FOUNTAIN JR ,  TONG QIN-YI

IPC: H01L27/00 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

Abstract: PROBLEM TO BE SOLVED: To provide a method of three-dimensionally integrating elements such as singulated dies or wafers and an integrated structure having connected elements such as singulated dies or wafers.SOLUTION: Either or both of the die and wafer have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. The first and second contact structures can be exposed at bonding and is electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnect the first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, the first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect the first and second contact structures and provide electrical access to the interconnected first and second contact structures.

Abstract translation: 要解决的问题：提供一种三维集成诸如单个模具或晶片的元件的方法以及具有诸如单个模具或晶片的连接元件的一体化结构。 解决方案：晶片和晶片中的任一个或两者具有形成在其中的半导体器件。 具有第一接触结构的第一元件被结合到具有第二接触结构的第二元件。 第一和第二接触结构可以在结合时暴露，并且由于接合而电互连。 可以在接合之后蚀刻和填充通孔，以暴露并形成电互连以互连第一和第二接触结构并提供从表面到该互连的电接入。 或者，第一接触结构和/或第二接触结构在接合时不暴露，并且通孔在接合之后进行蚀刻和填充，从而电连接第一和第二接触结构并提供对互连的第一和第二接触结构的电接触。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012199556A

公开(公告)日：2012-10-18

申请号：JP2012094996

申请日：2012-04-18

Applicant: Ziptronix Inc ,  ジプトロニクス・インコーポレイテッド

Inventor： PAUL M ENQUIST

IPC: H01L25/065 ,  H01L31/04 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L25/07 ,  H01L25/18 ,  H01L27/00

CPC classification number: H01L21/76898 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/48091 ,  H01L2924/00013 ,  H01L2924/01057 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of integrating devices and an integrated device.SOLUTION: An element may include one of a substrate used for heat radiation, impedance matching, or RF separation, an antenna, and a matching network formed of a passive element, and is directly adhered to a semiconductor device including a substrate 20. After that, a remaining part of the semiconductor device is exposed by removing a part of the substrate 20, and a first heat radiation substrate can be adhered to the remaining part of the semiconductor device. A wire can be formed on a surface on which the semiconductor device is exposed. A via can be formed in a device region via the semiconductor device. The wiring can be formed between the device region and a contact structure.

Abstract translation: 要解决的问题：提供一种集成设备和集成设备的方法。 解决方案：元件可以包括用于散热，阻抗匹配或RF分离的基板之一，天线和由无源元件形成的匹配网络，并且直接粘附到包括基板20的半导体器件 之后，通过去除衬底20的一部分来暴露半导体器件的剩余部分，并且可以将第一散热衬底粘附到半导体器件的其余部分。 可以在其上露出半导体器件的表面上形成导线。 可以经由半导体器件在器件区域中形成通孔。 布线可以在器件区域和接触结构之间形成。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012186481A

公开(公告)日：2012-09-27

申请号：JP2012090162

申请日：2012-04-11

Applicant: Ziptronix Inc ,  ジプトロニクス・インコーポレイテッド

Inventor： TONG QIN-YI ,  PAUL M ENGQUIST ,  ANTHONY SCOT ROSE

IPC: H01L21/02 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/98 ,  H01L23/522

CPC classification number: H01L21/76251 ,  B23K20/02 ,  H01L21/481 ,  H01L24/09 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/90 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/80801 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81014 ,  H01L2224/81136 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/83095 ,  H01L2224/8319 ,  H01L2224/8334 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83907 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05124 ,  H01L2224/05147

Abstract: PROBLEM TO BE SOLVED: To bond wafers to each other at a low temperature or an ambient temperature without using external pressure.SOLUTION: This invention relates to a bonded device structure, and the bonded device structure includes: a first substrate having a first pair of metal bonding pads connecting with a device or a circuit and a first nonmetallic region located adjacent to the metal bonding pads on the first substrate 10; a second substrate having a second pair of metal bonding pads located adjacent to the first pair of metal bonding pads connecting with the device or the circuit and a second nonmetallic region located adjacent to the metal bonding pads on the second substrate 13; and a contact bonded boundary surface between the first and second pairs of metal bonding pads which is formed by contact-bonding the first nonmetallic region to the second nonmetallic region. At least one of the first and second substrates may be elastically deformed.

Abstract translation: 要解决的问题：在低温或环境温度下将晶片彼此接合而不使用外部压力。 粘合装置结构技术领域本发明涉及粘结装置结构，并且粘合装置结构包括：第一基板，其具有与装置或电路连接的第一对金属焊盘和与金属接合相邻的第一非金属区域 第一基板10上的焊盘; 第二衬底，具有位于与所述器件或所述电路连接的所述第一对金属焊盘相邻的第二对金属焊盘和与所述第二衬底13上的所述金属焊盘相邻的第二非金属区域; 以及通过将第一非金属区域接触到第二非金属区域而形成的第一和第二对金属接合焊盘之间的接触接合边界面。 第一和第二基板中的至少一个可能弹性变形。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2012156514A

公开(公告)日：2012-08-16

申请号：JP2012043454

申请日：2012-02-29

Applicant: Ziptronix Inc ,  ジプトロニクス・インコーポレイテッド

Inventor： PAUL M ENQUIST

IPC: H01L21/331 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/20 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/98 ,  H01L27/00 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/737

CPC classification number: H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: PROBLEM TO BE SOLVED: To provide a device having high integration density and a device integration method.SOLUTION: Surfaces of first and second workpieces are each polished to a surface roughness of about 5 to 10Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1 to 10 times the surface non-planarity of the material on which they are formed. A number of devices may be bonded together, and the devices may be different types of devices or different technologies.

Abstract translation: 要解决的问题：提供具有高集成度的器件和器件集成方法。 解决方案：将第一和第二工件的表面抛光至约5至10埃的表面粗糙度。 第一和第二工件的抛光表面粘合在一起。 将第三工件的表面抛光至表面粗糙度。 第三工件的表面被接合到接合的第一和第二工件上。 第一，第二和第三工件可以各自是具有在一个表面上形成的薄材料，优选以晶片形式形成的半导体器件。 将薄的材料抛光至所需的表面粗糙度，然后粘结在一起。 薄材料可以各自具有其形成它们的材料的表面非平面度的约1至10倍的厚度。 多个设备可以结合在一起，并且设备可以是不同类型的设备或不同的技术。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：AU2005227167B2

公开(公告)日：2010-12-23

申请号：AU2005227167

申请日：2005-02-23

Applicant: ZIPTRONIX INC

Inventor： FOUNTAIN GAIUS G JR ,  ENQUIST PAUL M ,  PETTEWAY CARL T

IPC: H01L23/495

Abstract: A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.

公开(公告)号：WO2017200717A1

公开(公告)日：2017-11-23

申请号：PCT/US2017/029187

申请日：2017-04-24

Applicant: ZIPTRONIX, INC.

Inventor： UZOH, Cyprian, Emeka ,  SITARAM, Arkalgud, R. ,  ENQUIST, Paul

IPC: H01L23/12 ,  H01L23/00 ,  H01L21/56

Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

Abstract translation: 在各种实施例中，公开了一种用于形成结合结构的方法。 该方法可以包括将第一集成器件管芯安装到载体。 安装后，第一个集成器件管芯可以变薄。 该方法可以包括在第一集成器件管芯的暴露表面上提供第一层。 第一层的至少一部分可以被去除。 第二个集成器件管芯可以直接连接到第一个集成器件管芯，而不需要中间粘合剂。