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公开(公告)号:JP5324051B2
公开(公告)日:2013-10-23
申请号:JP2007089019
申请日:2007-03-29
Applicant: 新光電気工業株式会社
Inventor: 和弘 小林
CPC classification number: H01L21/6835 , H01L21/4853 , H01L21/563 , H01L23/49816 , H01L24/48 , H01L24/81 , H01L24/85 , H01L2221/68345 , H01L2224/16225 , H01L2224/48227 , H01L2224/8121 , H01L2224/81815 , H01L2224/85444 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15174 , H01L2924/15311 , H05K1/113 , H05K3/108 , H05K3/205 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/09563 , Y10T29/49155 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are laminated and insulating layers are laminated as a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128. A second electrode pad 132 is formed to be wider in a radial direction (a planar direction) than an outside diameter of a first electrode pad 130 on a boundary surface between a first insulating layer 121 and a second insulating layer 123. The second electrode pad 132 formed to be wider than the first electrode pad 130 is provided between the first electrode pad 130 and a via 134.
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公开(公告)号:JP4975581B2
公开(公告)日:2012-07-11
申请号:JP2007265615
申请日:2007-10-11
Applicant: 新光電気工業株式会社
Inventor: 和弘 小林
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公开(公告)号:JP5289880B2
公开(公告)日:2013-09-11
申请号:JP2008247687
申请日:2008-09-26
Applicant: 新光電気工業株式会社
IPC: H05K3/46
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公开(公告)号:JP5203108B2
公开(公告)日:2013-06-05
申请号:JP2008234621
申请日:2008-09-12
Applicant: 新光電気工業株式会社
CPC classification number: H05K3/188 , H01L21/563 , H01L21/568 , H01L23/49816 , H01L23/49822 , H01L24/16 , H01L2224/13099 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81385 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/12042 , H01L2924/15311 , H05K1/0313 , H05K1/09 , H05K1/113 , H05K3/205 , H05K3/244 , H05K3/282 , H05K3/383 , H05K3/4682 , H05K2201/09472 , H05K2201/09563 , H05K2203/0361 , Y10T29/4916 , Y10T156/10 , H01L2924/00 , H01L2224/0401
Abstract: A wiring board includes a pad exposed from an opening portion of an outermost insulating layer. The pad includes: a first metal layer a surface of which is exposed from the wiring board; a second metal layer provided on the first metal layer and formed of a material effective in preventing a metal contained in a via inside the board from diffusing into the first metal layer; and a third metal layer provided between the second metal layer and the via, and formed of a material harder to be oxidized than that of the second metal layer. The thickness of the third metal layer is relatively thick, and is preferably selected to be three times or greater than a thickness of the second metal layer. A side surface of the third metal layer and a surface of the third metal layer to which the via is to be connected are roughed.
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公开(公告)号:JP4881211B2
公开(公告)日:2012-02-22
申请号:JP2007105965
申请日:2007-04-13
Applicant: 新光電気工業株式会社
CPC classification number: H01L21/6835 , H01L21/4853 , H01L21/4857 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/48 , H01L24/81 , H01L24/85 , H01L2221/68345 , H01L2224/13099 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/48227 , H01L2224/8121 , H01L2224/81815 , H01L2224/85444 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01088 , H01L2924/014 , H01L2924/15174 , H01L2924/15311 , H01L2924/351 , H05K1/113 , H05K3/205 , H05K3/28 , H05K3/4007 , H05K3/4644 , H05K2201/0367 , H05K2201/0376 , H05K2201/09563 , H05K2201/2072 , Y10T29/49156 , Y10T29/49165 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
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公开(公告)号:JP5315447B2
公开(公告)日:2013-10-16
申请号:JP2012193205
申请日:2012-09-03
Applicant: 新光電気工業株式会社
CPC classification number: H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To improve the adhesion strength of a pad by inhibiting the occurrence of cracks and thereby improving the reliability as a product and contributing to the improvement of the connection reliability with a mother board and the like. SOLUTION: A wiring board 10 includes: a pad 11P; an outmost insulation layer 12 covering the pad 11P, allowing a surface of the pad 11P to be exposed from its surface, and provided with an opening VH1, from which a rear surface of the pad 11P is exposed, on its rear surface; a via formed in the opening VH1; and a wiring layer 13 formed on the rear surface of the insulation layer 12 and connected to the via 13. The pad 11P is embedded in the insulation layer 12, and a side surface and the rear surface of the pad 11P contact with the insulation layer 12. The pad 11P has a first metal layer 21, a second metal layer 22 provided on the first metal layer 21, and a third metal layer 23 provided on the second metal layer 22 and connected to the via 13. A peripheral part of the second metal layer 22 retracts inward from a peripheral part of the pad 11P. COPYRIGHT: (C)2013,JPO&INPIT
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公开(公告)号:JP4800253B2
公开(公告)日:2011-10-26
申请号:JP2007098458
申请日:2007-04-04
Applicant: 新光電気工業株式会社
CPC classification number: H05K3/4007 , H01L21/4846 , H01L21/4853 , H01L21/6835 , H01L2224/13 , H01L2224/16225 , H01L2924/00014 , H01L2924/15174 , H05K1/113 , H05K3/205 , H05K3/28 , H05K3/423 , H05K3/4682 , H05K2201/09436 , H05K2201/09472 , H05K2203/0369 , H05K2203/0376 , H05K2203/0733 , H01L2224/0401
Abstract: A method of manufacturing a wiring substrate comprises: a first step of forming, on a support plate, an electrode pad made of metal; a second step of etching the support plate in such a manner that the support plate has a shape which includes a projection portion to be contacted with the electrode pad; a third step of forming, on the surface of the support plate, an insulating layer for covering the electrode pad; a fourth step of forming, on the surface of the insulating layer, a conductive pattern to be connected to the electrode pad; and, a fifth step of removing the support plate.
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公开(公告)号:JP5580374B2
公开(公告)日:2014-08-27
申请号:JP2012184119
申请日:2012-08-23
Applicant: 新光電気工業株式会社
CPC classification number: H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
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