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公开(公告)号：KR101799014B1
公开(公告)日：2017-11-20
申请号：KR1020100131984
申请日：2010-12-21
Applicant: 에스케이하이닉스 주식회사 , 고려대학교 산학협력단
IPC: G11C11/4093 , G11C11/4074 , G11C7/10 , G11C5/14 , H03K19/0185
Abstract: 본발명의버퍼회로는전원전압및 출력노드사이에연결된로드부, 출력노드및 제 1 노드사이에연결되어입력신호를입력받는입력신호수신부, 제 1 노드및 접지전압사이에연결된소스부및 출력노드의출력신호에응답하여바이어스전압을출력하는제어부를포함하고, 소스부는바이어스전압에따라제 1 노드에서상기접지전압으로흐르는전류량이조절된다.
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公开(公告)号：KR1020130028530A
公开(公告)日：2013-03-19
申请号：KR1020110092149
申请日：2011-09-09
Applicant: 에스케이하이닉스 주식회사 , 고려대학교 산학협력단
CPC classification number: G11C5/063 , G11C7/1066 , G11C7/22 , G11C2207/2272
Abstract: PURPOSE: A multichip package and an operating method thereof are provided to maximally secure a data valid period by outputting data without an overlap. CONSTITUTION: A first through via(TSV1) transmits an external clock signal generated in a central processing unit(310) to a plurality of semiconductor memory devices(320,330,340). A second through via(TSV2) is connected to the plurality of semiconductor memory devices and transmits a common internal clock signal generated in one semiconductor memory device to the remaining semiconductor memory devices. A third through via(TSV3) transmits data outputted from the plurality of semiconductor devices to a central processing unit. [Reference numerals] (310) Central processing unit; (320) First semiconductor memory device; (330) Second semiconductor memory device; (340) Third semiconductor memory device
Abstract translation: 目的：提供多芯片封装及其操作方法，通过输出数据而不重叠来最大限度地确保数据有效期。 构成：第一通孔（TSV1）将在中央处理单元（310）中生成的外部时钟信号发送到多个半导体存储器件（320,330,340）。 第二通孔（TSV2）连接到多个半导体存储器件，并将在一个半导体存储器件中产生的公共内部时钟信号发送到剩余的半导体存储器件。 第三通孔（TSV3）将从多个半导体器件输出的数据发送到中央处理单元。 （附图标记）（310）中央处理单元; （320）第一半导体存储器件; （330）第二半导体存储器件; （340）第三半导体存储器件
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公开(公告)号：KR1020120070426A
公开(公告)日：2012-06-29
申请号：KR1020100131984
申请日：2010-12-21
Applicant: 에스케이하이닉스 주식회사 , 고려대학교 산학협력단
IPC: G11C11/4093 , G11C11/4074 , G11C7/10 , G11C5/14 , H03K19/0185
CPC classification number: G11C11/4093 , G11C5/147 , G11C7/1006 , G11C11/4074 , H03K19/018528
Abstract: PURPOSE: A buffer circuit, a duty correction circuit, and an active decoupling capacitor are provided to secure the stability of a ground voltage and a power voltage by reducing the variation of a PVT of a clock signal. CONSTITUTION: A load unit(100) is connected between a power voltage and an output node. An input signal receiving unit(200) is connected between an output node and a first node and receives an input signal. A source unit(300) is connected to the first node and a ground voltage. A control unit(400) outputs a bias voltage in response to an output signal of the output node. The source unit controls an amount of currents flowing from the first node to a ground voltage according to the bias voltage.
Abstract translation: 目的：提供缓冲电路，占空比校正电路和有源去耦电容，以通过减少时钟信号的PVT的变化来确保接地电压和电源电压的稳定性。 构成：负载单元（100）连接在电源电压和输出节点之间。 输入信号接收单元（200）连接在输出节点和第一节点之间，并接收输入信号。 源单元（300）连接到第一节点和接地电压。 控制单元（400）响应于输出节点的输出信号输出偏置电压。 源单元根据偏置电压控制从第一节点流向接地电压的电流量。
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公开(公告)号：KR100983485B1
公开(公告)日：2010-09-27
申请号：KR1020080069755
申请日：2008-07-17
Applicant: 고려대학교 산학협력단
IPC: H03K23/00
Abstract: 본 발명은 주파수 체배 기술을 개시한다. 즉, 하모닉 록 방지 블록을 이용하여 입력 클럭의 일정 주기 상에 존재하는 불필요한 펄스를 삭제시킨 후, 입력 클럭 상에 존재하는 당해 펄스 신호를 기준 클럭의 일정 주기 내에 포함되도록 제어함으로써 보다 넒은 대역폭을 갖는 입력 클럭이 들어오더라도 하모닉 록을 사전에 방지하고 또한, 채비 클럭의 급격한 변화에 따라 발생되는 내부 잡음을 디더링부를 이용하여 제거시켜 지연고정루프 기반의 주파수 체배 시스템 및 그 체배 방법을 구현한다.
체배 클럭, 하모닉 록 방지 블록, 듀얼 루프, 디더링부-
公开(公告)号：KR1020100013023A
公开(公告)日：2010-02-09
申请号：KR1020080074503
申请日：2008-07-30
Applicant: 고려대학교 산학협력단
CPC classification number: H03L7/0812 , G06F1/06 , H03K5/135 , H03K5/1534 , H03L7/089
Abstract: PURPOSE: A frequency multiplication system and a control method thereof are provided to prevent malfunction by preventing a control voltage from falling from a reset state to a ground value. CONSTITUTION: A delay locked loop(100) changes a source clock inputted from the outside into a first delay clock group and a second delay clock group. A time error comparator(200) self-corrects an irregular delay pulse width by controlling one delay clock rising edge or falling edge selected among the delay clocks. A frequency multiplier(300) extracts a plurality of set clocks by applying a first set clock group and a second set clock group to a preset multiplication ratio. The frequency multiplier generates a multiplication clock by combining the plurality of extracted set clocks.
Abstract translation: 目的：提供一种倍频系统及其控制方法，以通过防止控制电压从复位状态下降到接地值来防止故障。 构成：延迟锁定环（100）将从外部输入的源时钟改变为第一延迟时钟组和第二延迟时钟组。 时间误差比较器（200）通过控制在延迟时钟中选择的一个延迟时钟上升沿或下降沿来自校正不规则的延迟脉冲宽度。 倍频器（300）通过将第一组时钟组和第二组时钟组施加到预设乘法比来提取多个设定时钟。 倍频器通过组合多个提取的设置时钟来产生乘法时钟。
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Patent Agency Ranking
公开(公告)号：KR1020100009068A
公开(公告)日：2010-01-27
申请号：KR1020080069756
申请日：2008-07-17
Applicant: 고려대학교 산학협력단
IPC: H03L7/00
CPC classification number: H03L7/0814 , H03L7/0891 , H03L7/0895 , H03L7/095 , H03L7/0995
Abstract: PURPOSE: A delay locked loop and a control method thereof are provided to synchronizing an output clock of the delay locked loop with a reference input clock by reducing a static phase error due to a charge pump current mismatch. CONSTITUTION: A differential transducer(100) generates a differential clock and a differential reverse clock. A voltage control delay unit(200) generates a first multi phase clock group including (N+1) multi phase clocks based on the 0-th reference multiple clock extracted from the differential clock. A harmonic lock prevention block(300) changes four multiple phase clock to the force control signal. A phase detector(400) transmits an up signal and a down signal to a charge pump(500). The charge pump generates the control voltage matched with the up signal and the down signal. A lock detector(600) grasps the normal locking of the delay locked loop. An auxiliary charge pump(700) generates an inner up control voltage and an inner down control voltage.
Abstract translation: 目的：提供延迟锁定环及其控制方法，以通过减少由于电荷泵电流失配引起的静态相位误差来将延迟锁定环的输出时钟与参考输入时钟同步。 构成：差分换能器（100）产生差分时钟和差分反向时钟。 电压控制延迟单元（200）基于从差分时钟提取的第0个参考多个时钟生成包括（N + 1）个多相位时钟的第一多相位时钟组。 谐波锁定防止块（300）将四个多相时钟改变为力控制信号。 相位检测器（400）将上行信号和下降信号发送到电荷泵（500）。 电荷泵产生与上升信号和下降信号匹配的控制电压。 锁定检测器（600）掌握延迟锁定环的正常锁定。 辅助电荷泵（700）产生内部上升控制电压和内部下降控制电压。
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公开(公告)号：KR1020120045413A
公开(公告)日：2012-05-09
申请号：KR1020100106932
申请日：2010-10-29
Applicant: 고려대학교 산학협력단
CPC classification number: G01K7/25 , G01K7/01 , G01K15/005
Abstract: PURPOSE: A temperature sensing circuit and a sensing method thereof are provided to reduce errors of a temperature measurement result by nonlinear characteristic and to enhance the accuracy and resolution of the measurement result. CONSTITUTION: A temperature sensing circuit comprises a first oscillator(301), a second oscillator(303), and a temperature information generating unit(307). The first oscillator generates a fist periodical signal. The second oscillator generates a second periodical signal. A frequency of the second periodical signal becomes higher as a temperature is increased. The temperature information generating unit generates temperature information by using a difference between the frequencies of first and second periodical signals.
Abstract translation: 目的：提供一种温度检测电路及其检测方法，以减少非线性特性对温度测量结果的误差，提高测量结果的精度和分辨率。 构成：温度检测电路包括第一振荡器（301），第二振荡器（303）和温度信息产生单元（307）。 第一个振荡器产生第一个周期信号。 第二振荡器产生第二周期信号。 随着温度的升高，第二周期信号的频率变高。 温度信息生成单元通过使用第一和第二周期信号的频率之间的差来生成温度信息。
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公开(公告)号：KR101013920B1
公开(公告)日：2011-02-14
申请号：KR1020080074503
申请日：2008-07-30
Applicant: 고려대학교 산학협력단
Abstract: 본 발명은 주파수 체배 기술을 개시한다. 즉, 불규칙한 지연차를 갖는 다중 지연 클럭을 비교하고, 다중 지연 클럭 간의 지연 미스매치를 자기 보정하여 규칙적이며 일정한 지연 펄스 폭을 형성하는 저지터의 다중 지연 클럭을 생성 및 주파수 체배하는 주파수 체배 시스템 및 그 제어 방법을 구현함으로써, 제어 전압이 리셋될 때 그라운드 값으로 떨어지는 것을 방지하여 오동작의 발생 가능성을 제거됨과 더불어 해당 체배비에 맞게 양상된 깨끗한 체배 클럭을 다수개 생성하고, 이 생성된 체배 클럭을 제공받은 임베디드 시스템 혹은 임베디드 프로세서의 고정밀 성능 향상을 고조시킨다.
지연고정루프, 시간 오차 비교기, 주파수 체배기, 자기 보정-
公开(公告)号：KR1020100009067A
公开(公告)日：2010-01-27
申请号：KR1020080069755
申请日：2008-07-17
Applicant: 고려대학교 산학협력단
IPC: H03K23/00
CPC classification number: H03K5/00006 , H03K5/135 , H03L7/0812
Abstract: PURPOSE: A delay lock loop based frequency multiple system and a multiplying method thereof are provided to delete an unnecessary pulse at a constant cycle of an input clock using a harmonic lock prevention block. CONSTITUTION: A harmonic lock prevention block(100) compares a pulse signal of an input clock with a constant cycle of a reference clock. A delay lock loop(200) controls the phase difference between the input clock and the reference clock using a force control signal. The delay lock loop generates a multiple control clock by changing an up signal or down signal to a control voltage. A frequency multiplier(300) generates a multiple clock by multiplying the multiple control clock. A dual loop(400) positions the pulse signal existing in the constant cycle of the multiple clock at the constant cycle of the reference clock. A dithering unit(500) removes the internal noise from the multiple clock by switching the multiple clock before the change and the multiple clock after the change.
Abstract translation: 目的：提供一种基于延迟锁定环的频率多重系统及其乘法方法，以使用谐波锁定阻止块在输入时钟的恒定周期中删除不必要的脉冲。 构成：谐波锁定防止块（100）将输入时钟的脉冲信号与参考时钟的恒定周期进行比较。 延迟锁定环（200）使用力控制信号来控制输入时钟和参考时钟之间的相位差。 延迟锁定环通过将上升信号或下降信号改变为控制电压来产生多个控制时钟。 倍频器（300）通过乘以多个控制时钟来产生多个时钟。 双回路（400）将以多个时钟的恒定周期存在的脉冲信号定位在参考时钟的恒定周期。 抖动单元（500）通过在变化之前切换多个时钟并在更改之后切换多个时钟来从多个时钟消除内部噪声。
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公开(公告)号：KR1020080096969A
公开(公告)日：2008-11-04
申请号：KR1020070041956
申请日：2007-04-30
Applicant: 고려대학교 산학협력단
IPC: H03L7/06
CPC classification number: H03K5/00006 , H03K5/1534 , H03L7/0814 , H03L7/0891 , H03L7/095
Abstract: An apparatus and a method for delay locked loop based frequency multiplication solves a harmonic locking problem by using a lock controller without giving a specific signal of a control voltage in an initial operation. A voltage controlled delay line has N delay stages. A delay locked loop(110) locks the last clock signal(Bn) passing through the voltage controlled delay line(111) in the reference clock signal passing through the buffer edge(113) and generates N+1 differential clock signals(B0-Bn) distributed equally as much as the number N of the delay units from the reference clock signal in the locking state, and passes the differential clock signals through the buffer unit. An AND circuit(120) generates an output pulse from differential clock signals passing through the buffer unit which is the output signal of the delay locked loop. An edge combiner(140) synthesizes output pulses and generates the output clock with multiplied frequency.
Abstract translation: 用于基于延迟锁相环的倍频的装置和方法通过使用锁定控制器在初始操作中不给出控制电压的特定信号来解决谐波锁定问题。 电压控制延迟线具有N个延迟级。 延迟锁定环（110）锁定通过经过缓冲器边沿（113）的参考时钟信号中通过压控延迟线（111）的最后时钟信号（Bn），并产生N + 1个差分时钟信号（B0-Bn ）在锁定状态下从参考时钟信号分配等于延迟单元的数量N，并且通过缓冲器单元传递差分时钟信号。 AND电路（120）从通过作为延迟锁定环路的输出信号的缓冲单元的差分时钟信号产生输出脉冲。 边缘组合器（140）合成输出脉冲并以倍频产生输出时钟。
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