Abstract:
본 발명은 태양전지의 전면 전극에 관한 것으로, 본 발명의 실시예에 따른 태양전지의 전면 전극은 n형 반도체 기판(1)의 수광면에 배치되는 태양전지의 전면 전극에 있어서, 원형 또는 다각형 도트(dot) 형상으로 형성되고, 서로 이격 배치되는 다수의 금속도트(10), 및 금속도트(10)를 가로질러, 적어도 2개 이상의 금속도트(10)를 서로 연결하는 다수의 금속와이어(20)를 포함한다.
Abstract:
본 발명은 다중 입출력 통신 기술을 개시한다. 즉, 본 발명의 실시예에 따른 다중 입출력 중계 시스템 및 그 방법은 기요청된 실데이터를 주파수 용량 초과로 인하여 드롭시킨 제 2 셀의 제 2 기지국 대신에 제 1 셀의 제 1 기지국에 기할당된 주파수 용량 중 여분을 이용하여 제 1 셀에 위치한 제 1 중계기, 제 2 셀에 위치한 제 2 중계기와 순차적으로 연결된 하나 이상 선택된 사용자 통신 단말기에 전달되도록 신호 처리함으로써, 중계 통신에서의 끊김없는 실데이터의 입출력에 대한 신뢰성을 향상시키고, 셀 간의 기할당된 주파수 용량을 자동 조절하여 통화 봉쇄율 및 주파수 용량에 대한 활용도를 높인다. 제 1, 2 중계기, 제 1 기지국, 송수신 안테나 간섭, 필요전력
Abstract:
PURPOSE: A MIMO(Multiple Input Multiple Output) relay system and a method of the same are provided to enhance the availability about frequency capacities by automatically controlling the frequency capacities which is already assigned between cells. CONSTITUTION: The first base station(100) matches necessary power proportions of N pieces which is different to each other with user interference cancellation real data of N pieces by one-to-one for transmitting user interference elimination real data of N pieces to the first repeater which is located in the first cell. The first base station generates the first base station real data of N pieces which is different to each other by using antenna interference recognition and antenna interference recognizer/eliminator(130).
Abstract:
An apparatus and a method for block interleaving using a mixed radix system in an MB(Multi Band)-OFDM(Orthogonal Frequency Division Multiplexing) are provided to reduce power consumption, complexity, and time delay in an interleaving process and to comprise each cell of an array processor as a simple logic of two one-bit storage space and a switch by implementing an array processor structure. In a multi band orthogonal frequency division multiplexing communication system, an interleaving device(100) block-interleaves an input stream of M bit to be transmitted by a modular k. The interleaving device includes an array processor. The array processor has M cells composed of the array with k columns and an M/k rows. The array processor inputs the input stream from a right lower cell to a final cell of a left upper cell of the array processor in a horizontal direction. After a first bit of the input stream reaches the final cell, the output of the array processor is changed from the horizontal direction to the vertical direction and the interleaved output stream is generated.
Abstract:
PURPOSE: A decoding method for a system which uses raptor codes is provided to reduce the system load by reducing the calculation quantity. CONSTITUTION: A variable node remaining after the MP decipher of the raptor codes is established as a set Uv(ST10). The selected guess node and the free variable nodes are composed as a first group(ST20). Rest of the groups except the variable node are obtained(ST30). Two biggest groups are assigned to G1 and G2(ST40). A subgroup G10 or G11 satisfying the equation of the check node is selected(ST50). Group G20 or G21 satisfying the check node equation is selected by using the subgroup G20 about and G21(ST60).