公开(公告)号：KR101368972B1

公开(公告)日：2014-03-03

申请号：KR1020130040220

申请日：2013-04-12

Applicant: 국민대학교산학협력단

Inventor： 황준석 ,  안제엽 ,  서효준 ,  배학열 ,  김대환 ,  김동명

IPC: H01L21/66 ,  H01L29/786

CPC classification number: H01L22/12 ,  H01L22/30 ,  H01L29/78693

Abstract: A method for extracting state density in a band gap of an amorpous oxide semiconductor thin film transistor by using an optical differential ideality coefficient and a device thereof are provided. The method for extracting state density in a band gap of an amorpous oxide semiconductor thin film transistor includes a step of measuring a darkroom drain current from a darkroom according to a gate voltage and measuring a light reaction drain current according to the gate voltage by emitting light of a light source, a step of calculating a light reaction ideality coefficient and a darkroom ideality coefficient by using the light reaction drain current and the darkroom drain current, and a step of extracting the state density in the band gap of the thin film transistor based on the differentiation of the light reaction ideality coefficient and the darkroom ideality coefficient. The step of extracting the state density extracts genuine state density by de-embedding capacitance formed by free electrons. [Reference numerals] (AA) Start; (BB) End; (S310) Measure a darkroom drain current according to a gate voltage in a darkroom; (S320) Measure a light reaction drain current according to the gate voltage by emitting light of a light source; (S330) Calculate a darkroom ideality coefficient by using the darkroom drain current; (S340) Calculate a light reaction ideality coefficient by using the light reaction drain current; (S350) Calculate light reaction capacitance based on the differentiation of the light reaction ideality coefficient and the darkroom ideality coefficient; (S360) Extract state density from a band gap based on the light reaction capacitance

Abstract translation: 提供了一种通过使用光学差分理想系数提取氧化硅半导体薄膜晶体管的带隙中的状态密度的方法及其装置。 用于提取氧化硅半导体薄膜晶体管的带隙中的状态密度的方法包括根据栅极电压测量来自暗室的暗室漏极电流并根据栅极电压通过发光测量反射漏极电流的步骤 的光源，通过使用光反应漏极电流和暗室漏极电流来计算光反应理想系数和暗室理想系数的步骤，以及提取薄膜晶体管的带隙中的状态密度的步骤 关于光反应理想系数和暗室理想系数的差异。 提取状态密度的步骤通过解嵌入由自由电子形成的电容来提取真实状态密度。 （附图标记）（AA）开始; （BB）结束; （S310）根据暗室中的栅极电压测量暗室漏极电流; （S320）通过发射光源来测量根据栅极电压的光反应漏极电流; （S330）使用暗室漏电流计算暗室理想系数; （S340）使用光反应漏极电流计算光反应理想系数; （S350）基于光反射理想系数和暗室理想系数的差异，计算光反应电容; （S360）基于光反应电容从带隙提取状态密度

公开(公告)号：KR101531667B1

公开(公告)日：2015-06-26

申请号：KR1020140066080

申请日：2014-05-30

Applicant: 국민대학교산학협력단

Inventor： 김동명 ,  김대환 ,  안제엽 ,  배학열 ,  최현준 ,  황준석

IPC: H01L21/66 ,  H01L29/786

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L29/78672

Abstract: 본발명은다결정박막트랜지스터에서결정립계가존재하지않는경우의게이트-드레인, 게이트-소스의커패시턴스-전압특성과결정립계가존재하는경우의게이트-드레인, 게이트-소스의커패시턴스-전압특성의차를이용하여결정립계의위치에의존하는커패시턴스의변화()를추출하고최종적으로는결정립계의위치를계산을통해추출하는장치및 방법을제공하기위한것으로서, 결정립계가소자의채널내에존재하지않는경우의커패시턴스-전압특성및 결정립계가소자의채널내에존재하는경우의커패시턴스-전압특성을각각검출하는커패시턴스-전압특성검출모듈과, 상기커패시턴스-전압특성검출모듈에서검출된각각의커패시턴스-전압특성을서로비교하고그 결과의차를이용하여커패시턴스의변화()를추출하는커패시턴스변화추출부와, 상기커패시턴스변화추출부에서추출된커패시턴스의변화를이용하여소자의채널내 결정립계의위치를산출하는결정립경계위치산출부를포함하여구성되는데있다.

Abstract translation: 本发明是提供一种装置和方法，其通过使用栅极 - 漏极和栅极 - 源极的电容 - 电压特性的差异来提取取决于晶粒位置的电容的变化，当晶粒不是 存在于多晶硅薄膜晶体管中，并且当存在晶粒时使用栅极 - 漏极和栅极 - 源极的电容 - 电压特性的差异，并且最终通过计算提取晶粒的位置。 该装置包括：电容电压特性检测模块，用于当晶体存在于器件的沟道内时分别检测电容 - 电压特性;以及当晶粒不存在于器件的沟道中时的电容 - 电压特性; 电容变化提取单元，通过使用电容电压特性检测模块分别检测出的电容电压特性之差通过比较电容电压特性来提取电容的变化（C_gb.X_GB）; 以及晶界边界位置计算单元，通过使用由电容变化提取单元提取的电容的变化来计算器件的沟道内的晶粒的位置。

公开(公告)号：KR101427713B1

公开(公告)日：2014-08-07

申请号：KR1020130112514

申请日：2013-09-23

Applicant: 국민대학교산학협력단

Inventor： 김동명 ,  김대환 ,  최현준 ,  배학열 ,  황준석 ,  안제엽

IPC: H01L21/66 ,  H01L29/786

CPC classification number: H01L22/12 ,  H01L22/30 ,  H01L29/78693

Abstract: A method for extracting intrinsic subgap density of states of an amorphous oxide semiconductor thin film transistor using a channel conduction factor, and a device thereof are disclosed. The method for extracting the intrinsic subgap density of states of the amorphous oxide semiconductor thin film transistor according to an embodiment of the present invention comprises a step of measuring capacitance according to a gate voltage of the thin film transistor; a step of extracting a conduction factor of a channel according to the gate voltage using the measured capacitance; and a step of extracting intrinsic subgap density of states based on the conduction factor of the extracted channel. The step of extracting the intrinsic subgap density of states replaces a physical length between source and drain electrodes with a length of a variable of the conduction factor of the channel and extracts the intrinsic subgap density of states considering the conduction factor of the channel.

Abstract translation: 公开了一种使用沟道导通因数提取非晶氧化物半导体薄膜晶体管的本征子陷阱密度的方法及其装置。 根据本发明实施例的用于提取非晶氧化物半导体薄膜晶体管的本征子陷阱密度的方法包括根据薄膜晶体管的栅极电压测量电容的步骤; 使用测量的电容根据栅极电压提取沟道的导通因数的步骤; 以及基于提取的通道的导通因数来提取状态的内在子陷阱密度的步骤。 提取状态的固有子间隙密度的步骤取代了源极和漏极之间的物理长度，其长度为通道的导通因子的变量的长度，并且考虑通道的导通因数提取状态的内在子陷阱密度。

公开(公告)号：KR101557935B1

公开(公告)日：2015-10-08

申请号：KR1020140188932

申请日：2014-12-24

Applicant: 국민대학교산학협력단

Inventor： 김동명 ,  안제엽 ,  황준석 ,  이정민

IPC: H01L21/66

CPC classification number: H01L22/12

Abstract: 본발명은다결정박막트랜지스터에서결정립경계가존재하지않는경우의커패시턴스-전압특성과결정립경계가존재하는경우의커패시턴스-전압특성의차를이용하여결정립경계의위치에의존하여변하는공핍커패시턴스를통해유효한공핍영역의폭을구해최종적으로는결정립경계의위치를추출하는장치및 방법을제공하기위한것으로서, 결정립경계가채널내에존재하는소자의커패시턴스-전압특성을검출하는 C-V특성검출부와, 상기검출된커패시턴스-전압특성을기반으로공핍영역을형성할수 있는크기에해당하는게이트전압이인가되었을경우의커패시턴스값을추출하는커패시턴스값 추출부와, 상기추출된커패시턴스값으로부터결정립경계의위치에의존하여변하는공핍커패시턴스를분리추출하는공핍커패시턴스추출부와, 상기분리추출된공핍커패시턴스로부터유효한공핍영역의폭을산출하여공핍층의두께로부터결정립경계의수직방향위치를산출하는결정립계위치산출부를포함하여구성되는데있다.

Abstract translation: 本发明是提供一种通过利用晶界的位置变化的耗尽电容获得有效耗尽区的宽度来提取晶界位置的装置和方法，其使用电容 - 电压特性 在多晶薄膜晶体管中不存在晶界的情况和存在晶界的情况的电容 - 电压特性。 本发明的装置包括：C-V特性检测部，其检测在通道中存在晶界的装置的电容 - 电压特性; 电容值提取部，其根据检测出的电容电压特性，施加与能够形成耗尽区的振幅相对应的栅极电压的情况下提取电容值; 耗尽电容提取部，其根据所提取的电容值分离并提取根据晶界的位置而变化的耗尽电容; 以及晶界位置计算部分，通过从分离和提取的耗尽电容计算有效耗尽区的宽度，从耗尽区的厚度计算晶界的垂直位置。