公开(公告)号：KR101284751B1

公开(公告)日：2013-07-17

申请号：KR1020120006368

申请日：2012-01-19

Applicant: 단국대학교 산학협력단

Inventor： 강정원 ,  남현석 ,  노정진

IPC: H03K3/3565 ,  H03K5/156

CPC classification number: H03K3/3565 ,  H03K3/57 ,  H03K5/1565

Abstract: PURPOSE: A clock generating circuit is provided to have a small area and consume less electricity. CONSTITUTION: A clock generating circuit comprises a current supply unit (100), a trigger signal forming unit (200), a clock signal forming unit (300), and a duty ratio controller (400). A trigger signal forming unit forms a trigger signal by receiving current from the current supply unit. A clock signal forming unit forms a clock signal by being triggered to the trigger signal. A duty ratio controller controls the duty ratio of the clock signal by including at least one delayed elements which input the delay to the trigger signal forming unit by being getting the clock signal. [Reference numerals] (100) Current supply part; (200) Trigger signal forming part; (300) Clock signal forming part; (400) Duty ratio control part

Abstract translation: 目的：提供时钟发生电路具有小面积并消耗更少的电力。 构成：时钟发生电路包括电流源单元（100），触发信号形成单元（200），时钟信号形成单元（300）和占空比控制器（400）。 触发信号形成单元通过从电流供应单元接收电流来形成触发信号。 时钟信号形成单元通过触发触发信号形成时钟信号。 占空比控制器通过将至少一个延迟元件通过获取时钟信号而将延迟输入到触发信号形成单元来控制时钟信号的占空比。 （附图标记）（100）供电部; （200）触发信号形成部分; （300）时钟信号形成部分; （400）占空比控制部