-
-
公开(公告)号：KR1020080082826A
公开(公告)日：2008-09-12
申请号：KR1020070023627
申请日：2007-03-09
Applicant: 삼성전기주식회사
IPC: H03L7/08
CPC classification number: H03L7/099 , H03B5/1212 , H03B5/1228 , H03L7/18
Abstract: A phase locked loop having a stack structure for low power is provided to remove a power noise caused by a parasitic inductance generated in current mirroring by not using a current mirror circuit. A phase locked loop having a stack structure for low power includes a voltage controlled oscillator(120), and a divider(110). The voltage controlled oscillator is located on a ground terminal and an operation power terminal for supplying a predetermined operation power, and generates an oscillation signal. The divider is electrically coupled to the voltage controlled oscillator in series between the operation power terminal and the ground terminal. The divider generates a division signal which divides an oscillation signal of the voltage controlled oscillator. The voltage controlled oscillator and the divider form a transmission path of the operation current which flows between the operation power terminal and the ground terminal.
Abstract translation: 提供具有用于低功率的堆叠结构的锁相环，以通过不使用电流镜电路来消除由电流镜像中产生的寄生电感引起的功率噪声。 具有用于低功率的堆叠结构的锁相环包括压控振荡器（120）和分压器（110）。 压控振荡器位于接地端子和用于提供预定操作功率的操作电源端子，并产生振荡信号。 分压器电压耦合到操作电源端子和接地端子之间的压控振荡器。 分压器产生除电压振荡器的振荡信号的除法信号。 压控振荡器和分压器形成在操作电源端子和接地端子之间流动的工作电流的传输路径。
-
公开(公告)号：KR100691369B1
公开(公告)日：2007-03-09
申请号：KR1020050095747
申请日：2005-10-11
Applicant: 삼성전기주식회사
Abstract: A voltage controlled oscillator with body bias controlling is provided to obtain a gain at low power consumption and to prevent the degradation of performance due to the variation of process and temperature by sensing and feeding back an oscillation operation. A resonant circuit part(100) generates a resonant frequency according to a tuning voltage. A differential oscillation part(200) supplies energy to the resonant circuit part by being differentially cross-coupled to the resonant circuit part, and outputs first and second oscillation signals of phase difference of 180 degrees by oscillating the resonant frequency of the resonant circuit part, and includes first and second transistors controlling the level of the first and second oscillation signal constantly according to a body bias voltage. An output level detection part(300) detects the level of the first and second oscillation signal of the differential oscillation part, and supplies the body bias voltage to each body of the first and second transistors.
Abstract translation: 提供具有体偏置控制的压控振荡器以获得低功耗下的增益，并且通过感测和反馈振荡操作来防止由于过程和温度的变化而引起的性能退化。 谐振电路部分（100）根据调谐电压产生谐振频率。 微分振荡部（200）通过与谐振电路部分差分交叉耦合而向谐振电路部分提供能量，并通过振荡谐振电路部分的谐振频率来输出具有180度相位差的第一和第二振荡信号， 并且包括第一和第二晶体管，其根据体偏置电压恒定地控制第一和第二振荡信号的电平。 输出电平检测部分（300）检测差动振荡部分的第一和第二振荡信号的电平，并将体偏置电压提供给第一和第二晶体管的每个主体。
-
公开(公告)号：KR1020160090637A
公开(公告)日：2016-08-01
申请号：KR1020150010680
申请日：2015-01-22
Applicant: 삼성전기주식회사
CPC classification number: H05K1/186 , H05K1/0271 , H05K2201/0133 , H05K2201/0187 , H05K3/4626 , H05K1/0298 , H05K1/185 , H05K3/4697
Abstract: 인쇄회로기판및 그제조방법이개시된다.
Abstract translation: 公开了一种能够控制翘曲的印刷电路板及其制造方法。 印刷电路板包括：具有空腔的芯基板; 在腔中接收的装置; 以及形成在所述腔和所述器件之间的第一绝缘层。
-
公开(公告)号：KR1020110063006A
公开(公告)日：2011-06-10
申请号：KR1020090119924
申请日：2009-12-04
CPC classification number: H03L7/1806 , H03L2207/50
Abstract: PURPOSE: A digital phase-locked loop improving a loop delay is provided to reduce a delay on a closed loop by using multi page signals with difference phases. CONSTITUTION: A reference phase accumulating part(100) outputs a standard sampling phase value by sampling an accumulated value of a reference clock phase. A phase detector(200) detects a phase difference signal corresponding to the difference between a reference sampling phase value and the DCO sampling phase value. A digital loop filter(300) averages the phase difference signal by filtering the phase difference signal. A digital control oscillator(500) generates an oscillation signal based on an averaged phase difference signal. A DCO phase accumulator(600) generates a plurality of clock signals whose phases are delayed. A plurality of D-FFs are operated according to a plurality of clock signals.
Abstract translation: 目的：提供一种改善环路延迟的数字锁相环，通过使用具有差分相位的多页信号来减少闭环上的延迟。 构成：参考相位累积部分（100）通过对参考时钟相位的累积值进行采样来输出标准采样相位值。 相位检测器（200）检测与参考采样相位值和DCO采样相位值之间的差相对应的相位差信号。 数字环路滤波器（300）通过对相位差信号进行滤波来对相位差信号进行平均。 数字控制振荡器（500）基于平均的相位差信号产生振荡信号。 DCO相位累加器（600）产生相位延迟的多个时钟信号。 根据多个时钟信号来操作多个D-FF。
-
Patent Agency Ranking
公开(公告)号：KR1020100063941A
公开(公告)日：2010-06-14
申请号：KR1020080122325
申请日：2008-12-04
CPC classification number: H03L7/193 , H03B5/1231 , H03B5/24 , H03L7/099 , H03L7/1974
Abstract: PURPOSE: A low power frequency synthesizer is provided to directly connect an operating current transferring route of a demultiply circuit unit to a resonant coil of an oscillation circuit unit without a DC/DC converter. CONSTITUTION: A demultiply circuit unit(100) is connected between a power terminal and an operating current transferring route. The demultiply circuit unit demultiplies inputted oscillation signal. An oscillation circuit unit(200) includes an inductance circuit unit(210) including a resonant coil connected to the operating current transferring route and a capacitor circuit unit(220) connected parallel with the inductance circuit unit. The oscillation circuit unit includes a negative resistant unit(230) for supplying the negative resistance to oscillate to the inductance circuit unit and the capacitor circuit unit. An intermediate point of the resonant coil is connected to the operating current transferring route. Both ends of the resonant coil are connected to the demultiply circuit unit.
Abstract translation: 目的：提供一种低功率频率合成器，用于将不连续电路单元的工作电流传输路径直接连接到没有DC / DC转换器的振荡电路单元的谐振线圈。 构成：电力终端和工作电流传输路径之间连接多个电路单元（100）。 多分支电路单元对输入的振荡信号进行分频。 振荡电路单元（200）包括：电感电路单元（210），包括连接到工作电流传输路径的谐振线圈和与电感电路单元并联连接的电容器电路单元（220）。 振荡电路单元包括负电阻单元（230），用于提供负电阻以振荡到电感电路单元和电容器电路单元。 谐振线圈的中间点连接到工作电流传输路径。 谐振线圈的两端连接到多余电路单元。
-
公开(公告)号：KR1020160112345A
公开(公告)日：2016-09-28
申请号：KR1020150037959
申请日：2015-03-19
Applicant: 삼성전기주식회사
IPC: H01L23/48 , H01L23/488
CPC classification number: H01L23/562 , H01L23/367 , H01L23/3736 , H01L23/3737 , H01L23/481 , H01L23/488
Abstract: 본발명은, 몸체부와, 상기몸체부의표면에형성된비아및 상기비아내부에형성된충진부를포함하는휨방지부재를포함하는반도체칩을제시한다.
Abstract translation: 本发明提供一种半导体芯片，其包括主体部分，形成在主体部分的表面上的通孔，以及包括形成在通孔内部的填充单元的弯曲防止部件，从而使芯片的弯曲最小化。
-
公开(公告)号：KR101101447B1
公开(公告)日：2012-01-03
申请号：KR1020090119924
申请日：2009-12-04
CPC classification number: H03L7/1806 , H03L2207/50
Abstract: There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively.
-
公开(公告)号：KR100862509B1
公开(公告)日：2008-10-08
申请号：KR1020070023627
申请日：2007-03-09
Applicant: 삼성전기주식회사
IPC: H03L7/08
Abstract: 본 발명은 동작전압이 각각 다른 전압 제어 발진기와 분주기를 사용하는 위상 동기 루프에서, DC/DC 컨버터를 사용하지 않고 전압 제어 발진기와 분주기를 스택구조로 형성하여 전력 소모를 효율적으로 개선하고, 칩크기를 컴팩트하게 구성할 수 있는 저전력용 스택 구조 위상 동기 루프에 관한 것이다.
본 발명은 사전에 설정된 동작 전원을 공급하는 동작 전원단과 접지단 사이에 위치하여 발진신호를 생성하는 전압 제어 발진기와, 상기 동작 전원단과 상기 접지단 사이에, 상기 전압 제어 발진기와 상호 전기적으로 직렬 연결되어 상기 전압 제어 발진기로부터의 발진신호를 분주한 분주신호를 생성하는 분주기를 포함하고, 상기 전압 제어 발진기 및 분주기는 상기 동작 전원단과 접지단 사이에 흐르는 동작 전류의 전달 경로를 형성하는 것을 특징으로 한다.
저전력(low power), 스택 구조(stack structure), 전압 제어 발진기(voltage controlled oscillator), 분주기(divider), 위상 동기 루프(Phase Locked Loop)-
公开(公告)号：KR100691371B1
公开(公告)日：2007-03-12
申请号：KR1020050098319
申请日：2005-10-18
Applicant: 삼성전기주식회사
IPC: H03B5/08
Abstract: A voltage controlled oscillator for low power is provided to perform a stable oscillation by controlling an oscillation frequency according to a tuning voltage of a low power system. A resonant circuit part(100) is connected to a power supply voltage, and generates a resonant frequency according to a tuning voltage. A differential oscillation part(200) includes first and second transistors(M10,M20) outputting an oscillation signal by oscillating the resonant frequency of the resonant circuit part by being differentially cross-coupled to the resonant circuit part. A peak detection part(300) detects a peak value of the oscillation signal of the differential oscillation part, and outputs a peak detection voltage by adding the power supply voltage and a detected voltage. An inverter(400) converts a control voltage with a lower voltage level than the tuning voltage into the tuning voltage having a voltage level of the peak detection voltage according to the peak detection voltage.
Abstract translation: 通过根据低功率系统的调谐电压控制振荡频率来提供用于低功率的压控振荡器以执行稳定的振荡。 谐振电路部分（100）连接到电源电压，并根据调谐电压产生谐振频率。 微分振荡部分（200）包括通过与谐振电路部分差分交叉耦合而振荡谐振电路部分的谐振频率来输出振荡信号的第一和第二晶体管（M10，M20）。 峰值检测部分（300）检测差动振荡部分的振荡信号的峰值，并且通过将电源电压和检测电压相加来输出峰值检测电压。 逆变器（400）根据峰值检测电压将具有比调谐电压更低的电压电平的控制电压转换为具有峰值检测电压的电压电平的调谐电压。
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.02 seconds)
