公开(公告)号：KR100525967B1

公开(公告)日：2005-11-03

申请号：KR1020030062552

申请日：2003-09-08

Applicant: 삼성전자주식회사

Inventor： 가재환

IPC: H01L27/04

Abstract: 용량이 증가된 커패시터를 포함하는 반도체 장치 및 반도체 장치의 제조 방법이 개시되어 있다. 반도체 기판 상에 형성된 절연막 패턴, 상기 절연막의 소정 부위에 구비되어 상기 기판과 접속하는 금속 플러그, 상기 금속 플러그와 인접하는 절연막이 상기 기판이 노출되지 않을 정도로 제거된 형상을 갖고, 상기 금속 플러그의 측면을 노출시키는 고리형의 하부 전극용 콘택홀, 상기 하부 전극용 콘택홀의 내부 표면 및 상기 금속 플러그 외부 표면에 형성된 하부 전극, 상기 하부 전극 및 상기 절연막 상부면에 형성된 유전막 및 상기 유전막 상에 상부 전극을 구비하는 반도체 장치를 제공한다. 상기 하부 전극의 표면적 증가로 커패시터의 축적 용량이 증가되는 효과가 있다.

公开(公告)号：KR1020040050644A

公开(公告)日：2004-06-16

申请号：KR1020020078506

申请日：2002-12-10

Applicant: 삼성전자주식회사

Inventor： 정희근 ,  이덕형 ,  가재환

IPC: H01L21/24

Abstract: PURPOSE: A method for manufacturing a semiconductor device having a silicide layer is provided to simplify the manufacturing process and easily carry out a contact forming process by forming a silicide barrier pattern having a single deposition structure. CONSTITUTION: A silicide barrier pattern having a single deposition structure is formed on a silicon substrate(30) for partially exposing the silicon substrate. A thin film containing predetermined material for a silicidation is formed on the upper surface of the resultant structure. A heat treatment is carried out on the resultant structure for transforming the thin film of the first region into a silicide layer(34a). The thin film of the second region is removed from the resultant structure for partially exposing the silicide barrier pattern. The exposed silicide barrier pattern is removed. An insulating layer(36a) is formed on the resultant structure. The first and second contact hole(38a,38b) are formed in the insulating layer for partially exposing the silicon substrate and the silicide layer, respectively.

Abstract translation: 目的：提供一种用于制造具有硅化物层的半导体器件的方法，以简化制造工艺，并且通过形成具有单个沉积结构的硅化物阻挡图案容易地进行接触形成工艺。 构成：在用于部分暴露硅衬底的硅衬底（30）上形成具有单一沉积结构的硅化物屏障图案。 在所得结构的上表面上形成含有用于硅化的预定材料的薄膜。 对所得结构进行热处理，将第一区域的薄膜转换成硅化物层（34a）。 从所得结构中除去第二区域的薄膜，以部分地暴露硅化物阻挡图案。 去除暴露的硅化物屏障图案。 在所得结构上形成绝缘层（36a）。 第一和第二接触孔（38a，38b）分别形成在绝缘层中，以分别暴露硅衬底和硅化物层。

公开(公告)号：KR1020020073822A

公开(公告)日：2002-09-28

申请号：KR1020010013685

申请日：2001-03-16

Applicant: 삼성전자주식회사

Inventor： 가재환

IPC: H01L27/108

Abstract: PURPOSE: A capacitor of a metal-insulator-metal structure and a method for fabricating the same are provided to prevent leakage current by forming uniformly a dielectric layer and improving a step coverage. CONSTITUTION: A lower electrode layer and a photoresist layer are sequentially coated on the first interlayer dielectric(100) on which a contact plug(102) is formed. A photoresist pattern is formed to define a lower electrode(104) on the photoresist layer. The lower electrode layer is etched by using the photoresist pattern as an etch mask and the lower electrode(104) is formed thereby. The second interlayer dielectric(106) is formed on the lower electrode(104). An aperture(108) is formed by etching the second interlayer dielectric(106). A dielectric layer(112) is formed on a whole surface of the above structure by using a chemical vapor deposition method. The dielectric layer(112) is formed by an oxide layer, a nitride layer, and a mixed layer of the oxide and the nitride. An upper electrode(114) is formed thereon. The upper electrode(114) is formed by a metal layer, a metal oxide layer or a mixed layer of the metal and the metal oxide.

Abstract translation: 目的：提供一种金属 - 绝缘体 - 金属结构的电容器及其制造方法，以通过均匀地形成介电层并提高台阶覆盖来防止漏电流。 构成：下电极层和光致抗蚀剂层依次涂覆在其上形成接触插塞（102）的第一层间电介质（100）上。 形成光致抗蚀剂图案以在光致抗蚀剂层上限定下电极（104）。 通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻下电极层，由此形成下电极（104）。 第二层间电介质（106）形成在下电极（104）上。 通过蚀刻第二层间电介质（106）形成孔（108）。 通过使用化学气相沉积法在上述结构的整个表面上形成电介质层（112）。 电介质层（112）由氧化物层，氮化物层和氧化物和氮化物的混合层形成。 在其上形成上电极（114）。 上部电极（114）由金属层，金属氧化物层或金属与金属氧化物的混合层构成。

公开(公告)号：KR1020070075017A

公开(公告)日：2007-07-18

申请号：KR1020060003269

申请日：2006-01-11

Applicant: 삼성전자주식회사

Inventor： 가재환

IPC: H01L27/108

CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L28/40

Abstract: A semiconductor device having an MIM capacitor is provided to increase the area of an electrode by vertically connecting at least one capacitor in parallel without increasing the area of the electrode. A first electrode(100) is formed on a semiconductor substrate. A first dielectric layer(201) is formed on the first electrode. A second electrode(130) is formed on the first dielectric layer. A first capacitor(A) is composed of the first electrode, the first dielectric layer and the second electrode. A second dielectric layer(231) is formed on the second electrode. A third electrode(160) is formed on the second dielectric layer. A second capacitor(B) is composed of the second electrode, the second dielectric layer and the third electrode. A third dielectric layer(261) is formed on the third electrode. A fourth electrode(190) is formed on the third dielectric layer. A third capacitor(C) is composed of the third electrode, the third dielectric layer and the fourth electrode. The first electrode is electrically connected to the third electrode through a first via. The second electrode is electrically connected to the fourth electrode through a second via. The first, second and third capacitors are interconnected in parallel. The first, second, third and fourth electrodes can include copper. The first, second and third dielectric layers can be made of silicon nitride.

Abstract translation: 提供具有MIM电容器的半导体器件，以通过垂直连接至少一个电容器而不增加电极的面积来增加电极的面积。 第一电极（100）形成在半导体衬底上。 第一电介质层（201）形成在第一电极上。 在第一电介质层上形成第二电极（130）。 第一电容器（A）由第一电极，第一电介质层和第二电极组成。 第二电介质层（231）形成在第二电极上。 第三电极（160）形成在第二电介质层上。 第二电容器（B）由第二电极，第二电介质层和第三电极构成。 第三电介质层（261）形成在第三电极上。 第四电极（190）形成在第三电介质层上。 第三电容器（C）由第三电极，第三电介质层和第四电极构成。 第一电极通过第一通孔电连接到第三电极。 第二电极通过第二通孔电连接到第四电极。 第一，第二和第三电容器并联连接。 第一，第二，第三和第四电极可以包括铜。 第一，第二和第三电介质层可以由氮化硅制成。

公开(公告)号：KR1020040080637A

公开(公告)日：2004-09-20

申请号：KR1020030015502

申请日：2003-03-12

Applicant: 삼성전자주식회사

Inventor： 가재환

IPC: H01L27/108

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent short between a plate electrode and a contact plug and to secure photo-misalign margin by forming a spacer at both sidewalls of an insulating layer and a bit line contact hole. CONSTITUTION: A plurality of cell transistors(220) are formed on a substrate(100). The first interlayer dielectric(240) is formed on the cell transistor and provided with a storage node contact pad(260) and a bit line contact pad(280). A plurality of cell capacitors are formed on the first interlayer dielectric and provided with storage electrodes(360) and a dielectric film(380a) and a plate electrode(400a). The second interlayer dielectric is formed on the resultant structure. An insulating layer(480) is formed at end parts of the plate electrode. Spacers(500) are formed at both sidewalls of the insulating layer and a bit line contact hole. The third insulating layer(540a) is formed on the resultant structure. A plurality of bit line plugs(600) are formed in the bit line contact hole to connect the bit line contact pad.

Abstract translation: 目的：提供一种半导体器件及其制造方法，以防止板状电极和接触插塞之间的短路，并且通过在绝缘层和位线接触孔的两个侧壁处形成间隔物来确保光学不对准边缘。 构成：在衬底（100）上形成多个单元晶体管（220）。 第一层间电介质（240）形成在单元晶体管上，并具有存储节点接触焊盘（260）和位线接触焊盘（280）。 在第一层间电介质上形成多个电池电容器，并设置有存储电极（360）和电介质膜（380a）和平板电极（400a）。 在所得结构上形成第二层间电介质。 在平板电极的端部形成有绝缘层（480）。 间隔物（500）形成在绝缘层的两个侧壁和位线接触孔处。 在所得结构上形成第三绝缘层（540a）。 在位线接触孔中形成多个位线插头（600），以连接位线接触垫。

公开(公告)号：KR1019980005951A

公开(公告)日：1998-03-30

申请号：KR1019960020844

申请日：1996-06-11

Applicant: 삼성전자주식회사

Inventor： 가재환

IPC: H01L21/66

公开(公告)号：KR1019970063610A

公开(公告)日：1997-09-12

申请号：KR1019960004449

申请日：1996-02-24

Applicant: 삼성전자주식회사

Inventor： 가재환 ,  김동석

IPC: H01L21/66

Abstract: 시편의 관찰 도중에 관찰 부위에 존재하는 파티클을 제거할 수 있도록 공기 흡입구를 반도체 소자 분석 장치의 현미경이 개시되었다. 본 발명은 빛이 통과할 수 있도록 가운데에 통로가 형성된 원통, 상기 통로의 단부에 부착된 대물렌즈를 구비하는 것을 특징으로 하는 반도체 소자 분석 장치의 현미경에 있어서, 상기 통로와 상기 원통의 외주면 사이에 상기 통로와 같은 방향으로 형성되고 상기 대물렌즈와 인근한 부위에서 외부와 연통되는 공기 흡입구를 더 구비한 것을 특징으로 하는 반도체 소자 분석 장치의 현미경을 제공한다. 본 발명에 의하면 현미경을 통하여 시편을 관찰할 경우에 관찰 부위에서 파티클이 발견되더라도 공기 흡입구를 통하여 공기를 흡입함으로써 파티클 제거할 수 있다. 따라서, 관찰 도중에 작업자가 직접 파티클을 제거할 수 있어 수율 및 작업 능률을 향상시킬 수 있다.

公开(公告)号：KR100791080B1

公开(公告)日：2008-01-03

申请号：KR1020070006947

申请日：2007-01-23

Applicant: 삼성전자주식회사

Inventor： 가재환

IPC: H01L21/60 ,  H01L23/48 ,  H01L23/58

CPC classification number: H01L24/05 ,  H01L21/76834 ,  H01L23/53214 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/85201 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device having a metal pad structure and a method for fabricating the same are provided to prevent generation of electrical short circuit between bonding wires formed on metal pad structures. A protective insulating layer(120) is formed on an upper surface of a substrate(100). A plurality of metal pad structures(130a) penetrate the protective insulating layer. The metal pad structures are separated from each other. The metal pad structures have upper surfaces which are positioned at a level higher than a level of the protective insulating layer. A plurality of insulating barrier spacers(140) are formed on sidewalls of the metal pad structures. The insulating barrier spacers have top surfaces which are positioned at a level higher than a level of the metal pad structures.

Abstract translation: 提供具有金属焊盘结构的电子器件及其制造方法，以防止在金属焊盘结构上形成的接合线之间产生电短路。 在基板（100）的上表面上形成保护绝缘层（120）。 多个金属焊盘结构（130a）穿透保护绝缘层。 金属垫结构彼此分离。 金属焊盘结构具有位于比保护绝缘层的高度高的高度的上表面。 在金属垫结构的侧壁上形成多个绝缘阻挡隔离物（140）。 绝缘阻挡间隔物具有位于比金属焊盘结构的高度高的高度的顶表面。

公开(公告)号：KR1020050025735A

公开(公告)日：2005-03-14

申请号：KR1020030062552

申请日：2003-09-08

Applicant: 삼성전자주식회사

Inventor： 가재환

IPC: H01L27/04

Abstract: A semiconductor device and a method of manufacturing the same are provided to improve capacitance by forming a lower electrode on a metal plug as well as in a contact hole. A semiconductor device includes a semiconductor substrate(100), an insulating pattern(104,108) with metal plugs(110) for contacting the substrate, contact holes(112) for exposing partially sidewalls of the metal plug, a lower electrode, a dielectric film(122) on the storage node electrode, and an upper electrode(124) on the dielectric film. The lower electrode(120) is formed along an inner surface of the contact hole and further formed on the metal plug.

Abstract translation: 提供半导体器件及其制造方法，以通过在金属插塞以及接触孔中形成下部电极来改善电容。 半导体器件包括半导体衬底（100），具有用于接触衬底的金属插头（110）的绝缘图案（104,108），用于暴露金属插塞的部分侧壁的接触孔（112），下电极，电介质膜（ 122），以及电介质膜上的上电极（124）。 下电极（120）沿着接触孔的内表面形成并进一步形成在金属插塞上。

公开(公告)号：KR1020030061158A

公开(公告)日：2003-07-18

申请号：KR1020020001697

申请日：2002-01-11

Applicant: 삼성전자주식회사

Inventor： 김승환 ,  가재환

IPC: H01L21/60

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: PURPOSE: A semiconductor device having bonding pads and a method for manufacturing the same are provided to be capable of improving the reliability of the device. CONSTITUTION: A semiconductor device is provided with a semiconductor substrate(31), an interlayer dielectric(33) located on the semiconductor substrate, the first metal pad(35a) having a bonding region(47) and a probing region(45), located on the interlayer dielectric, the second metal pad(41a) overlaid on the upper portion of the bonding region of the first metal pad, a conductive plug(39a) located between the first and second metal pad, and an insulating layer(37) located at the resultant structure for exposing the second metal pad and the probing region of the first metal pad through an opening portion(42).

Abstract translation: 目的：提供具有接合焊盘的半导体器件及其制造方法，以能够提高器件的可靠性。 构成：半导体器件设置有半导体衬底（31），位于半导体衬底上的层间电介质（33），第一金属焊盘（35a）具有接合区域（47）和探测区域（45），位于 在层间电介质上，覆盖在第一金属焊盘的接合区域的上部的第二金属焊盘（41a），位于第一和第二金属焊盘之间的导电插塞（39a）和位于 在所述结构中，通过开口部分露出第二金属焊盘和第一金属焊盘的探测区域。