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公开(公告)号：KR101771619B1
公开(公告)日：2017-08-28
申请号：KR1020110011608
申请日：2011-02-09
Applicant: 삼성전자주식회사
IPC: G11C16/04 , G11C16/08 , H01L27/115
CPC classification number: G11C16/0483 , G11C16/0466 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582
Abstract: 본발명의실시예에따른불휘발성메모리장치는, 기판과복수의비트라인들사이에연결되고, 선택라인들에의해서선택되는복수의셀 스트링들을포함하는메모리셀 어레이, 그리고상기선택라인들각각을적어도 2개의방향에서구동하는게이팅회로를포함한다.
Abstract translation: 根据本发明实施例的非易失性存储器件包括：存储器单元阵列，连接在衬底和多个位线之间并且包括通过选择线选择的多个单元串; 和一个至少在两个方向上驱动的门控电路。
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公开(公告)号：KR101739059B1
公开(公告)日：2017-05-24
申请号：KR1020110011609
申请日：2011-02-09
Applicant: 삼성전자주식회사
IPC: G11C16/30 , G11C16/04 , G11C16/08 , H01L27/115 , G11C11/56
CPC classification number: H01L27/11582 , G11C11/5621 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/1157
Abstract: 본발명은반도체메모리장치에관한것으로, 구체적으로불휘발성메모리장치에관한것이다. 본발명의실시예에따른불휘발성메모리장치는기판과직교하는방향으로적층된복수의메모리셀들을포함하는메모리셀 어레이; 워드라인들을통하여상기메모리셀 어레이에연결된행 선택회로; 및상기워드라인들에제공될전압들을발생하는전압발생회로를포함하며, 상기전압발생회로는목표전압레벨까지단계적으로증가시키는방식으로상기전압들을발생한다. 본발명의실시예에따른불휘발성메모리장치는일정한라이징슬롭을갖는구동신호들을메모리셀 어레이에제공할수 있다. 따라서, 읽기마진감소에의한신뢰성의하락이방지될수 있다.
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公开(公告)号：KR1020170118291A
公开(公告)日：2017-10-25
申请号：KR1020160045672
申请日：2016-04-14
Applicant: 삼성전자주식회사
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1048 , G06F11/1068 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/52
Abstract: 본발명은스토리지장치에관한것이다. 본발명의스토리지장치는, 불휘발성메모리장치, 그리고외부의호스트장치의요청에따라읽기커맨드를생성하여불휘발성메모리장치로전송하는컨트롤러를포함한다. 불휘발성메모리장치는읽기커맨드에응답하여읽기동작을수행하고, 읽혀진데이터를컨트롤러로출력하고, 그리고읽기동작의정보를내부의레지스터에저장한다.
Abstract translation: 存储装置技术领域本发明涉及存储装置。 本发明的存储设备包括非易失性存储设备和控制器，用于在外部主机设备的请求下产生读取命令并将读取的命令发送到非易失性存储设备。 非易失性存储器件响应于读取命令执行读取操作，将读取的数据输出到控制器，并将读取操作的信息存储在内部寄存器中。
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公开(公告)号：KR1020170004504A
公开(公告)日：2017-01-11
申请号：KR1020150094937
申请日：2015-07-02
Applicant: 삼성전자주식회사
CPC classification number: G11C16/0483 , G11C7/14 , G11C8/14 , G11C16/08 , G11C16/26 , G11C16/3427 , H01L27/11575 , H01L27/11582
Abstract: 본개시의일실시예에따른비휘발성메모리장치는복수의스트링들을포함하는메모리셀 어레이를포함할수 있다. 서로절연된 2개의접지선택라인들에의해서선택되는 2개의스트링들에각각포함되고제1 레벨에배치되는 2개의셀 트랜지스터들각각은, 로우드라이버로부터워드라인구동전압을서로상이한적어도 2개의경로들을통해서수신할수 있다.
Abstract translation: 如下提供存储器件。 存储单元阵列包括包括第一和第二串的串。 每个串包括接地选择晶体管和单元晶体管。 第一和第二接地选择线分别连接到第一串的第一接地选择晶体管的栅极和第二串的第二接地选择晶体管的栅极。 第一和第二单元栅极线分别连接到第一串的第一单元晶体管的栅极和第二串的第二单元晶体管的栅极。 第一互连单元将第一单元栅极线的第一部分电连接到第二单元栅极线的第一部分。 第二互连单元将第一单元栅极线的第二部分电连接到第二单元栅极线的第二部分。
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公开(公告)号：KR1020130080205A
公开(公告)日：2013-07-12
申请号：KR1020120000999
申请日：2012-01-04
Applicant: 삼성전자주식회사
IPC: G11C16/02 , G11C16/06 , H01L27/115
CPC classification number: G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11582 , H01L27/0688
Abstract: PURPOSE: A non-volatile memory device and a memory system including the same are provided to improve read performance by reducing a time for loading voltage to a word line. CONSTITUTION: A first NAND string (NS11) includes a first string selection transistor (SST), a first local ground selection transistor (LGST), a first global ground selection transistor (GGST), and a first memory cell. A second NAND string includes a second string selection transistor, a second local ground selection transistor, a second global ground selection transistor, and a second memory cell. Pass transistors (PT1-PT5) provide selected operation voltage to the first and the second string selection transistor, the first and the second local ground selection transistor, and the first and the second global selection transistor.
Abstract translation: 目的：提供一种非易失性存储器件和包括该非易失性存储器件的存储器系统，以通过减少加载到字线的电压的时间来提高读取性能。 构成：第一NAND串（NS11）包括第一串选择晶体管（SST），第一局部接地选择晶体管（LGST），第一全局接地选择晶体管（GGST）和第一存储单元。 第二NAND串包括第二串选择晶体管，第二本地接地选择晶体管，第二全局接地选择晶体管和第二存储单元。 通过晶体管（PT1-PT5）为第一和第二串选择晶体管，第一和第二局部地选择晶体管以及第一和第二全局选择晶体管提供选择的操作电压。
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Patent Agency Ranking
公开(公告)号：KR1020120091687A
公开(公告)日：2012-08-20
申请号：KR1020110011609
申请日：2011-02-09
Applicant: 삼성전자주식회사
IPC: G11C16/30 , G11C16/04 , G11C16/08 , H01L27/115 , G11C11/56
CPC classification number: H01L27/11582 , G11C11/5621 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/1157
Abstract: PURPOSE: A nonvolatile memory device is provided to prevent the degradation of reliability due to the reduction of read margin by providing driving signals with a constant rising slope to a memory cell array. CONSTITUTION: A memory cell array(110) includes a plurality of memory cells laminated in an orthogonal direction to a substrate. A row selection circuit(130) is connected to a memory cell array with word lines. A voltage generating circuit(120) generates voltages provided to word lines. The voltage generating circuit generates voltages which gradually increase to a target voltage level.
Abstract translation: 目的：提供一种非易失性存储器件，用于通过向存储单元阵列提供具有恒定上升斜率的驱动信号，以防止由于读取余量的降低导致的可靠性降低。 构成：存储单元阵列（110）包括沿与基板正交的方向层叠的多个存储单元。 行选择电路（130）与具有字线的存储单元阵列连接。 电压产生电路（120）产生提供给字线的电压。 电压产生电路产生逐渐增加到目标电压电平的电压。
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公开(公告)号：KR1020120091686A
公开(公告)日：2012-08-20
申请号：KR1020110011608
申请日：2011-02-09
Applicant: 삼성전자주식회사
IPC: G11C16/04 , G11C16/08 , H01L27/115
CPC classification number: G11C16/0483 , G11C16/0466 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582
Abstract: PURPOSE: A nonvolatile memory device and a driving method thereof are provided to improve the reliability of a read operation by setting a selection signal provided to a selection line. CONSTITUTION: A memory cell array(110) is connected between a substrate and a plurality of bit lines. A gating circuit drives each selection line in two directions and includes a first gating circuit(130) and a second gating circuit(135). The first gating circuit provides a string selection signal and a ground selection signal to one end of the selection lines and provides a word line voltage to a plurality of word lines. A second gating circuit provides the string selection signal and the ground selection signal to the other end of the selection line.
Abstract translation: 目的：提供非易失性存储器件及其驱动方法，通过设置提供给选择线的选择信号来提高读取操作的可靠性。 构成：存储单元阵列（110）连接在基板和多个位线之间。 门控电路在两个方向上驱动每个选择线，并且包括第一选通电路（130）和第二选通电路（135）。 第一选通电路向选择线的一端提供串选择信号和接地选择信号，并向多个字线提供字线电压。 第二选通电路将串选择信号和接地选择信号提供给选择线的另一端。
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公开(公告)号：KR101716713B1
公开(公告)日：2017-03-15
申请号：KR1020110048638
申请日：2011-05-23
Applicant: 삼성전자주식회사
CPC classification number: G11C5/025 , G11C5/145 , G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/12 , G11C16/30
Abstract: 본발명은플래시메모리장치및 그것의프로그램방법에관한것이다. 본발명의실시예에따른플래시메모리장치는 3차원구조를갖는메모리셀 어레이; 상기메모리셀 어레이로패스전압및 프로그램전압을제공하기위한전압발생기; 및프로그램동작시에프로그램루프별로패스전압의라이징슬롭을조절하는제어로직을포함한다. 본발명에의하면, 프로그램루프에따라패스전압의라이징슬롭을조절함으로, 프로그램속도를빠르게할 수있다.
Abstract translation: 存储器件及其编程方法，所述存储器件包括具有三维结构的存储单元阵列，被配置为向所述存储单元阵列提供通过电压和编程电压的电压发生器，以及配置为使所述上升的控制逻辑 程序运行期间程序循环的通过电压变量的斜率。 存储器件可以通过根据程序循环调整通过电压的上升沿来提高编程速度。
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公开(公告)号：KR1020120130588A
公开(公告)日：2012-12-03
申请号：KR1020110048638
申请日：2011-05-23
Applicant: 삼성전자주식회사
CPC classification number: G11C5/025 , G11C5/145 , G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/10
Abstract: PURPOSE: A flash memory device and a programming method thereof are provided to increase a program speed by controlling a rising slope of a pass voltage according to a program loop. CONSTITUTION: A voltage generator(1150) provides a pass voltage and a program voltage to a memory cell array. A control logic(1160) includes a voltage sloper(1165). The voltage sloper differently changes a rising slope of the pass voltage according to a program loop in a program operation. The voltage generator includes a voltage ramper(1153) and generates a pass voltage with a plurality of ramping levels. The voltage ramper generates the pass voltage with a plurality of ramping levels.
Abstract translation: 目的：提供闪速存储器件及其编程方法，以通过根据程序循环控制通过电压的上升斜率来增加编程速度。 构成：电压发生器（1150）向存储单元阵列提供通过电压和编程电压。 控制逻辑（1160）包括电压推移器（1165）。 在编程操作中，电压缓冲器根据程序循环不同地改变通过电压的上升沿。 电压发生器包括电压钳位器（1153）并产生具有多个斜坡电平的通过电压。 电压钳子产生具有多个斜坡电平的通过电压。
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公开(公告)号：KR101856130B1
公开(公告)日：2018-05-10
申请号：KR1020120000999
申请日：2012-01-04
Applicant: 삼성전자주식회사
IPC: G11C16/02 , G11C16/06 , H01L27/115
CPC classification number: G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11582
Abstract: 본발명은비휘발성메모리장치에관한것이다. 본발명의일 실시예에따른 3차원비휘발성메모리장치는제 1 스트링선택트랜지스터, 제 1 로칼접지선택트랜지스터, 제 1 글로벌접지선택트랜지스터, 제 3 기판으로부터수직방향으로적층된제 1 메모리셀들을포함하는제 1 낸드스트링과제 2 스트링선택트랜지스터, 제 2 로칼접지선택트랜지스터, 제 2 글로벌접지선택트랜지스터, 상기기판으로부터수직방향으로적층된제 2 메모리셀들을포함하는포함하는제 2 낸드스트링및 상기제 1 및제2 스트링선택트랜지스터, 상기제 1 및제 2 로칼접지선택트랜지스터, 상기제 1 및제 2 글로벌선택트랜지스터로동작전압을선택하여제공하는패스트랜지스터들을포함하는선택라인동작전압선택회로를포함하며, 상기제 1 글로벌선택트랜지스터및 제 2 글로벌선택트랜지스터는전기적으로연결되어있고, 상기제 1 로칼접지선택트랜지스터및 상기제 2 로칼접지선택트랜지스터는전기적으로분리되어있고, 상기제 1 글로벌접지선택트랜지스터및 상기제 2 글로벌접지선택트랜지스터는전기적으로연결된다.
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