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公开(公告)号：KR101559910B1
公开(公告)日：2015-10-15
申请号：KR1020090019359
申请日：2009-03-06
Applicant: 삼성전자주식회사
CPC classification number: G11C7/18 , G11C11/4087 , G11C2207/002
Abstract: 본발명은반도체메모리장치를공개한다. 이장치는워드라인들과비트라인쌍들각각의사이에연결된복수개의메모리셀을구비하는메모리셀 어레이, 컬럼선택신호에응답하여상기비트라인쌍들중 선택된비트라인쌍과로컬입출력라인쌍사이에데이터를전송하는비트라인선택부, 로컬글로벌입출력선택신호에응답하여상기로컬입출력라인쌍과글로벌입출력라인쌍사이에데이터를전송하는로컬글로벌입출력게이트부, 및외부로부터입력되는어드레스신호및 명령어에응답하여상기워드라인을구동하고, 상기컬럼선택신호를제1 전압으로활성화시키고, 상기로컬글로벌입출력선택신호를상기제1 전압레벨보다낮은제2 전압으로활성화시키는제어부를구비하는것을특징으로한다.
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公开(公告)号：KR100506531B1
公开(公告)日：2005-08-03
申请号：KR1020030079387
申请日：2003-11-11
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C29/34 , G11C2029/2602
Abstract: 본 발명은 반도체 메모리 장치의 병렬 비트 테스트 방법 및 병렬 비트 테스트 회로가 제공된다. 본 발명의 일실시예에 따른 반도체 메모리 장치의 병렬 비트 테스트 방법은 다수의 메모리 셀로부터 독출된 다수의 데이터를 제 1 테스트 모드로 테스트하거나, 다수의 메모리 셀로부터 독출된 다수의 데이터를 제 2 테스트 모드로 테스트하는 단계 및 제 1 테스트 모드의 출력과 제 2 테스트 모드의 출력을 확인하는 단계를 포함한다.
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公开(公告)号：KR100699406B1
公开(公告)日：2007-03-23
申请号：KR1020060006919
申请日：2006-01-23
Applicant: 삼성전자주식회사
IPC: G11C11/4063 , G11C11/409
CPC classification number: G11C7/22 , G11C11/4076 , G11C11/4096 , G11C7/12 , G11C11/4094
Abstract: A method and circuit for controlling a write recovery time in a semiconductor memory device are provided to minimize a clock noise by restricting an enable period of a control signal within a substantial recovery period. A circuit for controlling a write recovery time in a semiconductor memory device includes a start signal generator(110), a counter(120), an end signal generator(130), and a control signal generator(140). The start time generator generates a write recovery start signal corresponding to an input timing of last data, which is delayed from an automatic precharge write command input timing. The counter is enabled by a write recovery time control signal and counts a clock signal. The end time generator combines outputs signals of the counter and generates a write recovery time end signal. The control signal generator generates the write recovery time control signal, whose enable period is determined in response to the start and end signals.
Abstract translation: 提供一种用于控制半导体存储器件中的写恢复时间的方法和电路，用于通过将控制信号的使能周期限制在实质的恢复周期内来最小化时钟噪声。 一种用于控制半导体存储器件中的写恢复时间的电路，包括起始信号发生器（110），计数器（120），结束信号发生器（130）和控制信号发生器（140）。 起始时间发生器产生与从自动预充电写入命令输入定时延迟的最后数据的输入定时相对应的写恢复开始信号。 计数器由写恢复时间控制信号使能，并对时钟信号进行计数。 结束时间发生器组合计数器的输出信号并产生写恢复时间结束信号。 控制信号发生器产生写恢复时间控制信号，其响应于起始和结束信号确定其使能周期。
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公开(公告)号：KR1020050049260A
公开(公告)日：2005-05-25
申请号：KR1020030083178
申请日：2003-11-21
Applicant: 삼성전자주식회사
IPC: G11C8/12
Abstract: 본 발명은 반도체 메모리 장치를 공개한다. 이 반도체 메모리 장치는 테스트 제어 신호와 테스트 할 메모리 셀 어레이 블록을 선택하기 위한 테스트 제어 신호와 테스트 할 메모리 셀 어레이 블록을 선택하기 위한 테스트 어드레스 신호를 제공하는 테스트 제어 수단과, 테스트 모드인 경우에는, 상기 테스트 어드레스 신호를 디코딩하여 블록 선택 신호를 발생하고, 일반 모드인 경우에는 로우 어드레스 신호를 디코딩하여 블록 선택 신호를 발생하는 블록 선택 디코더를 구비하는 것을 특징으로 한다.
따라서 장치는 MRS(Mode Register Set)을 이용하여 테스트 모드를 선택하고, 반도체 메모리 장치가 테스트 모드로 선택된 경우에는 MRS(Mode Register Set)에서 제공하는 테스트 어드레스 신호를 이용하여 성능 테스트를 수행할 특정 메모리 셀 어레이 블록만을 인에이블할 수 있도록 하여, 테스트 시간을 획기적을 단축시켜 줄 수 있도록 한다.-
Patent Agency Ranking
公开(公告)号：KR1020040085906A
公开(公告)日：2004-10-08
申请号：KR1020030020759
申请日：2003-04-02
Applicant: 삼성전자주식회사
Inventor： 고승범
IPC: G11C11/409
CPC classification number: G11C11/4096 , G11C7/06 , G11C7/12 , G11C7/22 , G11C11/4091 , G11C11/4094
Abstract: PURPOSE: A semiconductor memory device capable of improving a write/read frequency in a write interrupt mode is provided to prevent the decrease of the write/read frequency in the write interrupt mode. CONSTITUTION: According to the semiconductor memory device(100), a memory cell array(110) includes memory cells arranged in a plurality of rows and in a plurality of columns. A write interrupt detection circuit(120) detects whether a write operation is performed after a write operation or a read operation is performed after a write operation, and outputs a control signal(PWICSL) as the detection result. A CSL disable circuit(130) outputs a CSL disable signal(PCSLDB) in response to the control signal from the write interrupt detection circuit. A CSL driver circuit(140) disables a column selection line enabled in response to the CSL disable signal from the CSL disable circuit.
Abstract translation: 目的：提供一种能够改善写入中断模式下的写入/读取频率的半导体存储器件，以防止在写入中断模式下写入/读取频率的降低。 构成：根据半导体存储器件（100），存储单元阵列（110）包括排列成多列和多列的存储单元。 写入中断检测电路（120）检测在写入操作之后执行写入操作或读取操作之后是否执行写入操作，并输出控制信号（PWICSL）作为检测结果。 响应于来自写入中断检测电路的控制信号，CSL禁止电路（130）输出CSL禁止信号（PCSLDB）。 CSL驱动器电路（140）响应于来自CSL禁止电路的CSL禁止信号而禁用启用的列选择线。
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公开(公告)号：KR1020100100457A
公开(公告)日：2010-09-15
申请号：KR1020090019359
申请日：2009-03-06
Applicant: 삼성전자주식회사
CPC classification number: G11C7/18 , G11C11/4087 , G11C2207/002
Abstract: PURPOSE: A semiconductor memory device is provided to transfer a voltage, which is lower than a pre-charged level of voltage in a global input-output line pair, to bit-lines by reducing a voltage applied to a local global input-output gate. CONSTITUTION: A memory cell array(10) includes a plurality of memory cells connected between each word-lines and bit-line pairs. A bit-line selection unit transfer data between selected bit-line pair from the bit-line pairs and local input-output pairs in response with a column selection signal. A local global input-output gate unit(40) transfers data between the local input-output line pairs and global input-output line pairs. A controller(70) drives the word-lines in response with an address signal and a command. The controller activates the column selection signal with a first voltage.
Abstract translation: 目的：提供一种半导体存储器件，用于通过降低施加到局部全局输入输出栅极的电压将低于全局输入 - 输出线对中的预充电电平的电压传送到位线 。 构成：存储单元阵列（10）包括连接在每个字线和位线对之间的多个存储单元。 位线选择单元响应于列选择信号，从位线对和本地输入 - 输出对之间的选定位线对之间传送数据。 本地全局输入输出门单元（40）在本地输入 - 输出线对与全局输入 - 输出线对之间传送数据。 响应于地址信号和命令，控制器（70）驱动字线。 控制器以第一电压激活列选择信号。
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公开(公告)号：KR1020080007940A
公开(公告)日：2008-01-23
申请号：KR1020060067205
申请日：2006-07-19
Applicant: 삼성전자주식회사
Abstract: A semiconductor memory device with split bank structure and a data input/output method thereof are provided to improve performance of the semiconductor memory device by changing bank structure and arrangement of an I/O sense amplifier of the semiconductor memory device. A memory bank(210) comprises a first sub-bank(220) and a second sub-bank(225). An internal input/output sense amplifier part(230) is located between the first sub-bank and the second sub-bank. An external input/output sense amplifier part(240) is located on the opposite side of the internal input/output sense amplifier of the second sub-bank. A plurality of first input/output lines(250) connects the internal input/output sense amplifier part and memory cells in the first sub-bank. A plurality of second input/output lines(291) connects the internal input/output sense amplifier part and memory cells in the second sub-bank. A plurality of third input/output lines(260) connects the internal input/output sense amplifier part and the external input/output sense amplifier part. The data of the memory cell in the first sub-bank is transmitted to the internal input/output sense amplifier part through the first input/output line, and is transmitted to the external input/output sense amplifier part through the third input/output line.
Abstract translation: 提供具有分割组结构及其数据输入/输出方法的半导体存储器件，以通过改变半导体存储器件的I / O读出放大器的存储体结构和排列来提高半导体存储器件的性能。 存储体（210）包括第一子库（220）和第二子库（225）。 内部输入/输出读出放大器部分（230）位于第一子行和第二子行之间。 外部输入/输出读出放大器部分（240）位于第二子库的内部输入/输出读出放大器的相对侧。 多个第一输入/输出线（250）连接第一子组中的内部输入/输出读出放大器部分和存储单元。 多个第二输入/输出线（291）连接第二子行中的内部输入/输出读出放大器部分和存储单元。 多个第三输入/输出线（260）连接内部输入/输出读出放大器部分和外部输入/输出读出放大器部分。 第一子库中的存储单元的数据通过第一输入/输出线传送到内部输入/输出读出放大器部分，并通过第三输入/输出线传输到外部输入/输出读出放大器部分 。
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公开(公告)号：KR100791001B1
公开(公告)日：2008-01-03
申请号：KR1020060106720
申请日：2006-10-31
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1063 , G11C7/106 , G11C7/22 , G11C8/18 , H03L7/0812
Abstract: A CAS latency circuit and a semiconductor memory device having the same are provided to generate a stable CAS latency signal in a high speed semiconductor memory device, regardless of the variation of PVT(Process, Voltage, Temperature) or using an external clock with high frequency. An internal read command signal generation part(110) generates an internal read command signal(PREAD) in response to a read command. A latency clock signal generation part(120) generates a plurality of latency clock signals. A latency signal generation part(130) receives the internal read command signal and the latency control clocks, and generates a latency signal by shifting the internal read command signal. The latency control clock generation part generates at least one first latency control clock having a constant margin to the internal read command signal by using a PREAD replica.
Abstract translation: 提供了一种CAS延迟电路和具有该CAS延迟电路的半导体存储器件，用于在高速半导体存储器件中产生稳定的CAS等待时间信号，而不管PVT（工艺，电压，温度）的变化或使用高频的外部时钟 。 内部读指令信号生成部（110）响应于读指令产生内读读指令信号（PREAD）。 等待时钟信号生成部（120）生成多个等待时钟信号。 等待时间信号产生部分（130）接收内部读命令信号和等待时间控制时钟，并通过移位内部读命令信号产生等待时间信号。 等待时间控制时钟生成部分通过使用PREAD副本来生成具有与内部读取命令信号的恒定余量的至少一个第一等待时间控制时钟。
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公开(公告)号：KR1020070066370A
公开(公告)日：2007-06-27
申请号：KR1020050127437
申请日：2005-12-22
Applicant: 삼성전자주식회사
Abstract: A column selection line generation circuit in a semiconductor memory device is provided to improve operation speed of the semiconductor memory device, by advancing enabling time of a column selection line during a normal operation. In a column selection line generation circuit of a semiconductor memory device generating a column selection signal for controlling the electrical connection between a specific bit line and a data input/output line, a decoding part(300) is enabled in response to a column selection line enable signal and generates an output signal responding to a column address specifying the bit line. A driving part(400) is driven to enable the column selection line in response to an output signal of the decoding part, and is disabled in response to the enabling of a repair signal so as to prevent the enabling of the column selection line.
Abstract translation: 提供半导体存储器件中的列选择线生成电路，通过在正常操作期间提前列选择线的使能时间来提高半导体存储器件的操作速度。 在产生用于控制特定位线和数据输入/输出线之间的电连接的列选择信号的半导体存储器件的列选择线生成电路中，响应于列选择线使能解码部分（300） 使能信号并响应指定位线的列地址产生输出信号。 驱动部分（400）被驱动以响应于解码部分的输出信号使列选择线响应于修复信号的使能而被禁用，从而阻止列选择线的使能。
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