公开(公告)号：KR1020090009561A

公开(公告)日：2009-01-23

申请号：KR1020070072951

申请日：2007-07-20

Applicant: 삼성전자주식회사

Inventor： 권용욱 ,  권철순 ,  채희일 ,  윤관영

IPC: H01L27/108

CPC classification number: H01L23/5223 ,  H01L21/7687 ,  H01L27/10808 ,  H01L27/10855

Abstract: A semiconductor device and a manufacturing method thereof are provided to form a capacitor by using metal patterns, thereby simplifying a manufacturing process and increasing capacitance. A gate electrode(114) is formed on a semiconductor substrate(100). An impurity region(105) is formed within the semiconductor substrate of both sides of the gate electrode. A contact plug(124) connected to the impurity region is formed. Subsequently, a capacitor(200) is formed on the outcome. The capacitor comprises first metal patterns(132a,152a) connected with the contact plug, second metal patterns(132b,152b) around the first metal patterns, and interlayer insulating films(140,160) filled between the first and second metal patterns. The first metal patterns configure a first electrode of the capacitor. The second metal patterns configure a second electrode of the capacitor.

Abstract translation: 提供半导体器件及其制造方法以通过使用金属图案形成电容器，从而简化制造工艺并增加电容。 在半导体衬底（100）上形成栅电极（114）。 在栅电极的两侧的半导体衬底内形成杂质区（105）。 形成连接到杂质区的接触插塞（124）。 随后，在结果上形成电容器（200）。 电容器包括与接触插塞连接的第一金属图案（132a，152a），围绕第一金属图案的第二金属图案（132b，152b）以及填充在第一和第二金属图案之间的层间绝缘膜（140,160）。 第一金属图案配置电容器的第一电极。 第二金属图案构成电容器的第二电极。

公开(公告)号：KR1020100068005A

公开(公告)日：2010-06-22

申请号：KR1020080126642

申请日：2008-12-12

Applicant: 삼성전자주식회사

Inventor： 권용욱 ,  권철순

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10882 ,  H01L27/10891

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to reduce manufacturing costs by forming an impurity layer on a semiconductor substrate. CONSTITUTION: An epitaxial layer is formed on a semiconductor substrate(110). A body is formed by etching the epitaxial layer after forming the epitaxial layer with a plurality of impurities by implanting ions. The body is vertical to the semiconductor substrate and includes a storage body(1050) comprised of a plurality of impurity layers and an access body(1070) formed on the storage body. Common lines(200) correspond to the storage body and are arranged while interposing the body. Word lines(400) are formed on the common lines in parallel and correspond to the access body.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过在半导体衬底上形成杂质层来降低制造成本。 构成：在半导体衬底（110）上形成外延层。 在通过注入离子形成具有多种杂质的外延层之后，通过蚀刻外延层形成主体。 本体与半导体衬底垂直，并且包括由多个杂质层组成的存储体（1050）和形成在存储体上的存取体（1070）。 公共线（200）对应于存储体并且在插入身体的同时被布置。 字线（400）平行地形成在公共线上并对应于存取体。

公开(公告)号：KR100809341B1

公开(公告)日：2008-03-05

申请号：KR1020070010703

申请日：2007-02-01

Applicant: 삼성전자주식회사

Inventor： 권용욱 ,  권철순 ,  정영천

IPC: H01L27/108 ,  H01L27/02 ,  H01L23/36

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C2213/79

Abstract: A nonvolatile memory device using a resistive element and a manufacturing method thereof are provided to implement high integration degree by using heat sink patterns. Plural variable resistance patterns(GST) are formed on a semiconductor substrate(110). Plural heat sink patterns(170) are formed at the same level as the variable resistance pattern. The heat sink patterns are connected to a ground voltage line(144). The ground voltage line is extended to a first direction. The heat sink pattern is extended to the first direction on the ground voltage line. The heat sink pattern includes a first sub heat sink pattern and a second sub heat sink pattern. The first sub heat sink pattern is formed on the ground voltage line to be extended to the first direction. The second sub heat sink pattern is extended to a second direction to be intersected with the first direction.

Abstract translation: 提供使用电阻元件的非易失性存储器件及其制造方法，以通过使用散热片图案实现高集成度。 多个可变电阻图案（GST）形成在半导体衬底（110）上。 多个散热片图案（170）形成在与可变电阻图案相同的水平。 散热片图案连接到地电压线（144）。 接地电压线延伸到第一方向。 散热器模式延伸到地电压线上的第一个方向。 散热器模式包括第一子散热器模式和第二子散热器模式。 第一副散热图案形成在接地电压线上以延伸到第一方向。 第二副散热图案延伸到与第一方向交叉的第二方向。

公开(公告)号：KR1020080073579A

公开(公告)日：2008-08-11

申请号：KR1020070012349

申请日：2007-02-06

Applicant: 삼성전자주식회사

Inventor： 정영천 ,  권철순 ,  유재민 ,  박재현 ,  권용욱 ,  윤인구 ,  임병철

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/67075 ,  H01L21/76838

Abstract: A flash memory having a bridge floating gate and a manufacturing method thereof are provided to reduce a TAT(Trap Assisted Tunneling) due to trapped electrons by replacing a tunnel oxide film with an air layer in a bridge-type floating gate. A device isolation film(110) defines an active region on a semiconductor substrate. A floating gate film(130a) is separated from the substrate and supported by the device isolation film. An inter-gate insulation film(150) covers the floating gate film. A control gate film(160) covers the inter-gate insulation film. A source or drain region is separated from the floating gate film in the substrate. An air layer(120a) is formed between the substrate and the floating gate film. A super thin oxide layer is formed on a surface of the floating gate film and the substrate, which are opposed to each other with the air layer between them.

Abstract translation: 提供具有桥式浮动栅极的闪存及其制造方法，以通过在桥式浮动栅极中用空气层代替隧道氧化物膜来减少由于捕获的电子而产生的TAT（陷阱辅助隧穿）。 器件隔离膜（110）限定半导体衬底上的有源区。 浮栅膜（130a）与衬底分离并由器件隔离膜支撑。 栅极间绝缘膜（150）覆盖浮栅膜。 控制栅膜（160）覆盖栅极间绝缘膜。 源极或漏极区域与衬底中的浮栅膜分离。 在基板和浮栅之间形成空气层（120a）。 在浮置栅极膜和基板的表面上形成超薄氧化物层，它们彼此相对，并且它们之间具有空气层。