公开(公告)号：KR1020020088476A

公开(公告)日：2002-11-29

申请号：KR1020010026956

申请日：2001-05-17

Applicant: 삼성전자주식회사

Inventor： 김남오

IPC: H01L27/108

Abstract: PURPOSE: A capacitor of semiconductor devices and a manufacturing method thereof are provided to improve a capacitance by increasing a surface area of a stacked storage node. CONSTITUTION: The capacitor comprises a storage contact plug(22) and a storage node(40) having H-shaped horizontal cross-section. The storage contact plug(22) is electrically connected to a pad plug(18) via an insulating layer(20) formed on a semiconductor substrate(10). The H-shaped storage node(40) is electrically connected to the storage contact plug(22). Also, the capacitor is composed of a capacitor dielectric film covered comformally to the storage node(40) and a plate electrode formed on the dielectric film. By forming a conductive layer on the insulating layer(20) having the storage contact plug(22) and patterning the conductive layer to expose the insulating layer(20), the H-shaped storage node(40) is formed.

Abstract translation: 目的：提供半导体器件的电容器及其制造方法，以通过增加层叠存储节点的表面积来提高电容。 构成：电容器包括具有H形水平横截面的存储接触插头（22）和存储节点（40）。 存储接触插头（22）经由形成在半导体衬底（10）上的绝缘层（20）电连接到焊盘插头（18）。 H形存储节点（40）电连接到存储接触插头（22）。 此外，电容器由与存储节点（40）类似地覆盖的电容器电介质膜和形成在电介质膜上的平板电极构成。 通过在具有存储接触插塞（22）的绝缘层（20）上形成导电层并图案化导电层以露出绝缘层（20），形成H形存储节点（40）。

公开(公告)号：KR1020010075943A

公开(公告)日：2001-08-11

申请号：KR1020000002898

申请日：2000-01-21

Applicant: 삼성전자주식회사

Inventor： 조종형 ,  김기영 ,  김남오

IPC: H01L27/108

Abstract: PURPOSE: A method for forming a capacitor is provided to remove the loss of impurities doped on the surface of the storage electrode, and to reduce fail ratio due to isolation of HSG(Hemi-Spherical Grain) formed on the surface of the storage electrode. CONSTITUTION: The method includes the four steps. The first step is to form a storage electrode pattern. The second step is to make HSG grow in the storage electrode pattern. A cleaning step is performed shortly after the second step. The third step is to deposit impurities on the surface layer of the storage electrode pattern on which the HSG is formed. The fourth step is to form a dielectric film on the storage electrode pattern in which the impurity is deposited. The third and the fourth steps are performed continually in a space by using an in situ method. During the third step, PH3 gas is inserted into the process chamber. During the fourth step, ammonia gas is inserted into the process chamber.

Abstract translation: 目的：提供一种用于形成电容器的方法，以消除在存储电极的表面上掺杂的杂质的损失，并且由于在存储电极的表面上形成的HSG（半球状晶粒）的隔离而降低失效率。 规定：该方法包括四个步骤。 第一步是形成存储电极图案。 第二步是使HSG在存储电极图案中生长。 在第二步之后不久进行清洁步骤。 第三步是在形成有HSG的存储电极图案的表面层上沉积杂质。 第四步骤是在其上沉积杂质的存储电极图案上形成电介质膜。 第三和第四步骤通过使用原位法在空间中连续进行。 在第三步骤中，将PH3气体插入处理室。 在第四步骤中，将氨气插入处理室。

公开(公告)号：KR1020000001504A

公开(公告)日：2000-01-15

申请号：KR1019980021803

申请日：1998-06-11

Applicant: 삼성전자주식회사

Inventor： 김남오 ,  김동일

IPC: H01L21/22

Abstract: PURPOSE: A diffusion furnace is provided to allow the sufficient amount of reactive gas to be supplied to a center of a wafer loaded on a boat. CONSTITUTION: The diffusion furnace for a semiconductor device formation comprises: an internal tube(42) in which a boat(4) is placed, wherein plural wafers(16) are loaded on the boat; an external tube(40) for retaining the internal tube; a reactive gate supply unit for supplying a reactive gas in the internal tube; and a reactive gas diffusion unit placed in an inner side of the internal tube, for making the supplied reactive gas diffused from the inner side of the internal tube(42) to the center of the internal tube(42).

Abstract translation: 目的：提供扩散炉以允许将足够量的反应气体供应到装载在船上的晶片的中心。 构成：用于半导体器件形成的扩散炉包括：其中放置船（4）的内管（42），其中多个晶片（16）装载在船上; 用于保持内管的外管（40）; 用于在内管中供应反应性气体的反应栅极供应单元; 以及放置在内管的内侧的反应性气体扩散单元，用于使供给的反应气体从内管（42）的内侧扩散到内管（42）的中心。

公开(公告)号：KR1020010028817A

公开(公告)日：2001-04-06

申请号：KR1019990041284

申请日：1999-09-27

Applicant: 삼성전자주식회사

Inventor： 김남오

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to improve reliability of a highly integrated semiconductor memory, by increasing capacitance of a capacitor caused by a broad surface area of a storage electrode. CONSTITUTION: A source/drain region and a gate electrode are formed on a substrate(1). An interlayer dielectric is stacked on the substrate. A storage electrode(10) electrically connected to the source region across a partial region of the interlayer dielectric is formed. A part of the upper surface of the storage electrode is etched by a desired depth to form a temporary pattern, so that a surface area of the storage electrode is increased without increasing an area of a wafer occupied by a capacitor.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，通过增加由存储电极的宽表面积引起的电容器的电容，来提高高度集成的半导体存储器的可靠性。 构成：在衬底（1）上形成源/漏区和栅电极。 层叠电介质层叠在基板上。 形成了跨过层间电介质的部分区域与源极区域电连接的存储电极（10）。 存储电极的上表面的一部分被蚀刻期望的深度以形成临时图案，使得存储电极的表面积增加而不增加由电容器占据的晶片的面积。

公开(公告)号：KR1020000026266A

公开(公告)日：2000-05-15

申请号：KR1019980043730

申请日：1998-10-19

Applicant: 삼성전자주식회사

Inventor： 김동일 ,  김남오

IPC: H01L21/22

Abstract: PURPOSE: A boat of semiconductor manufacturing apparatus is provided to operate in correct slots on performing preventive inspection. CONSTITUTION: A boat of semiconductor manufacturing apparatus includes an upper/lower plate(22b) maintaining a constant distance each other, a fixed bar(24) whose one end is combined to the upper plate and the other end is combined to the lower plate, slots(26) formed with a constant distance in the fixed bar(24) for inserted semiconductor wafers, a marking section(28) formed in a part of the fixed bar(24) and marks the turn of the slots in order from a predetermined turn of the fixed bar(24).

Abstract translation: 目的：提供半导体制造装置的船只，以便在执行预防性检查时在正确的槽中操作。 构成：半导体制造装置的船包括彼此保持恒定距离的上/下板（22b），一端结合到上板并且另一端组合到下板的固定杆（24） 在用于插入的半导体晶片的固定杆（24）中形成具有恒定距离的槽（26），形成在固定杆（24）的一部分中的标记部分（28），并且从预定的 转动固定杆（24）。

公开(公告)号：KR100643573B1

公开(公告)日：2006-11-13

申请号：KR1020000006377

申请日：2000-02-11

Applicant: 삼성전자주식회사

Inventor： 김기영 ,  김남오 ,  안중일

IPC: H01L27/108

Abstract: 본 발명은 반도체소자의 커패시터 제조방법을 개시한다. 이에 의하면, 하부전극용 다결정실리콘층의 패턴을 세정가스로 세정하고 다결정실리콘층의 표면에 반구형 입자를 성장한 후 이들을 불순물로 도핑하고 그 위에 유전막을 적층하는 공정을 하나의 튜브에서 처리한다.
따라서, 본 발명은 하부전극의 형성 후에 하부전극의 세정을 생략하고 유전막을 적층하므로 하부전극의 반구형 입자가 떨어짐으로 인한 비트라인의 불량을 방지할 수 있고 전체 제조공정을 단순화할 수 있다.

公开(公告)号：KR1020010097167A

公开(公告)日：2001-11-08

申请号：KR1020000021000

申请日：2000-04-20

Applicant: 삼성전자주식회사

Inventor： 김남오

IPC: H01L21/22

Abstract: 본 발명은 종형 확산장치의 배기구조를 개시한다. 이에 의하면, 종형 확산장치의 반응튜브와 로드록챔버 사이에 추가로 연통라인을 설치하고 이 연통라인에 에어밸브를 설치거나, 로드록챔버의 배기라인에 추가로 바라트론게이지(baratron gauge)와 같은 압력체크용 게이지를 설치하고 배기라인에 별도의 질소주입관을 연통하고 아울러 질소주입관에 압력보상용 피에조밸브(piezo valve)와 에어밸브를 설치할 수 있다.
따라서, 본 발명은 웨이퍼의 로딩/언로딩을 위해 반응튜브와 로드록챔버의 배기라인에 각각 설치된 바라트론게이지를 이용하여 이들 양측의 내부압력을 상압 이상의 압력으로 동일하게 만든 후 이들 양측을 서로 연통한 연통라인의 에어밸브를 개방하여 반응튜브와 로드록챔버의 내부압력을 실제적으로 동일하게 만들 수가 있다. 또한, 반응튜브와 로드록챔버가 저압상태에서도 각각의 바라트론게이지에 의해 이들 양측의 내부압력을 체크하고 로드록챔버의 내부압력을 체크한 바라트론게이지의 체크 값에 따라 제어부가 피에조밸브를 제어하여 피에조밸브를 거쳐 로드록챔버로 유입되는 질소가스의 유입량을 조절함으로써 이들 양측 사이의 압력차이를 보상하여 이들의 저압 내부압력을 동일하게 만들 수가 있다. 그 결과, 본 발명은 웨이퍼의 로딩/언로딩을 위해 반응튜브와 로드록챔버 사이의 셔터를 개방하더라도 갑작스런 대기의 와류 발생을 억제하여 웨이퍼의 파티클 오염을 방지할 수 있다.

公开(公告)号：KR1020010084597A

公开(公告)日：2001-09-06

申请号：KR1020000009767

申请日：2000-02-28

Applicant: 삼성전자주식회사

Inventor： 김남오 ,  김기영

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to reduce a manufacturing process time by changing a capacitor manufacturing process. CONSTITUTION: An interlayer dielectric is formed on a semiconductor substrate(200). A buried contact window is formed in the interlayer dielectric by etching selectively the interlayer dielectric(210). A polysilicon layer is formed on the whole face. A lower electrode is formed by etching selectively the polysilicon layer(220). An HSG(HemiSpheral Grain) is grown on an exposed portion of the lower electrode(230). PH3 is doped within the HSG(240). A dielectric layer is formed on the interlayer dielectric(250). A doped amorphous polysilicon layer is formed on the dielectric layer(260).

Abstract translation: 目的：提供一种用于制造半导体器件的电容器的方法，以通过改变电容器制造工艺来减少制造工艺时间。 构成：在半导体衬底（200）上形成层间电介质。 通过选择性地蚀刻层间电介质（210）在层间电介质中形成掩埋接触窗口。 整个面上形成多晶硅层。 通过选择性地蚀刻多晶硅层（220）形成下电极。 在下电极（230）的暴露部分上生长HSG（半球晶粒）。 PH3在HSG（240）内掺杂。 介电层形成在层间电介质（250）上。 在电介质层（260）上形成掺杂的非晶多晶硅层。

公开(公告)号：KR1020010081211A

公开(公告)日：2001-08-29

申请号：KR1020000006377

申请日：2000-02-11

Applicant: 삼성전자주식회사

Inventor： 김기영 ,  김남오 ,  안중일

IPC: H01L27/108

Abstract: PURPOSE: A method for fabricating a capacitor is to improve the process reliability by preventing the fail of a bit line generated due to the cleaning of a silicon substrate. CONSTITUTION: An isolation layer is formed at a field region of a silicon substrate to isolate an active region of the silicon substrate. A gate oxide layer is formed on the silicon substrate of the active region. A gate electrode is formed on a predetermined region of the gate oxide layer. A source and a drain are formed in the active region. A spacer of an insulating layer is formed on both sidewalls of the gate electrode. An interlayer dielectric is deposited on the entire surface of the silicon substrate including the gate electrode, thereby planarizing the surface of the silicon substrate. A through hole of the interlayer dielectric is formed to expose the source. A polysilicon layer is deposited on the interlayer dielectric and in the through hole. An oxide layer grown on the surface of the polysilicon layer is removed by cleaning the polysilicon layer, using a cleaning gas such as SF6.

Abstract translation: 目的：制造电容器的方法是通过防止由于硅衬底的清洁而产生的位线的故障来提高工艺可靠性。 构成：在硅衬底的场区形成隔离层以隔离硅衬底的有源区。 在有源区的硅衬底上形成栅氧化层。 栅电极形成在栅氧化层的预定区域上。 源极和漏极形成在有源区中。 绝缘层的间隔物形成在栅电极的两个侧壁上。 在包括栅电极的硅衬底的整个表面上沉积层间电介质，由此使硅衬底的表面平坦化。 层间电介质的通孔形成为露出源。 多晶硅层沉积在层间电介质和通孔中。 通过使用诸如SF 6的清洁气体清洗多晶硅层，去除在多晶硅层的表面上生长的氧化物层。