公开(公告)号：KR100746293B1

公开(公告)日：2007-08-03

申请号：KR1020060009588

申请日：2006-02-01

Applicant: 삼성전자주식회사

Inventor： 남장진 ,  전용원

IPC: H03K5/22

Abstract: A cascode-type current mode comparator, a receiving circuit having the same, and a semiconductor device having the same are provided to reduce an error rate of a receiving signal by improving an SNR(Signal-to-noise ratio). A receiving circuit(200) having a cascode-type current mode comparator includes a CMOS(Complementary Metal-Oxide Semiconductor) logic unit, first and second main transistors(MN,MP), a first cascode current source(Mpc), and a second cascode current source(Mnc). The CMOS logic unit converts the voltage of a voltage sensing node reflecting the difference between a standard electric current and a data electric current into an output signal of a CMOS level by being connected to the voltage sensing node. The first and second main transistors(MN,MP) are connected to the voltage sensing node and are turned on and off on the basis of the output signal. The first cascode current source(Mpc) supplies a first electric current from a first power to the voltage sensing node by being connected to a cascode of the first main transistor(MN). The second cascode current source(Mnc) supplies a second electric current from a second power to the voltage sensing node by being connected to a cascode of the second main transistor(MP).

Abstract translation: 提供了一种共源共栅型电流模式比较器，具有该共源共栅型电流模式比较器的接收电路以及具有该共源共栅型电流模式比较器的半导体器件，以通过提高SNR（信噪比）来降低接收信号的差错率。 具有共源共栅型电流模式比较器的接收电路（200）包括CMOS（互补金属氧化物半导体）逻辑单元，第一和第二主晶体管（MN，MP），第一共源共栅电流源（Mpc）和第二 共源共栅电流源（Mnc）。 CMOS逻辑单元通过连接到电压感测节点，将反映标准电流和数据电流之差的电压感测节点的电压转换为CMOS电平的输出信号。 第一和第二主晶体管（MN，MP）连接到电压感测节点并且基于输出信号导通和截止。 第一共源共栅电流源（Mpc）通过连接到第一主晶体管（MN）的共源共栅，从第一电源向电压感测节点提供第一电流。 第二共源共栅电流源（Mnc）通过连接到第二主晶体管（MP）的共源共栅，从第二电源向电压感测节点提供第二电流。

公开(公告)号：KR1020090088529A

公开(公告)日：2009-08-20

申请号：KR1020080013858

申请日：2008-02-15

Applicant: 삼성전자주식회사

Inventor： 이재열 ,  임정필 ,  김종선 ,  남장진

IPC: G09G3/36 ,  G09G3/20 ,  G02F1/133

CPC classification number: G09G3/3688 ,  G09G2330/021

Abstract: A data driving unit and a liquid crystal display including of the same are provided to prevent malfunction of the liquid crystal display by pre-charging and pre-discharging the data signal from the data driver selectively. In a data driving unit and a liquid crystal display including of the same, a charge sharing] switch(430) is connected with an output terminal of a first buffer(410) and the output of a second buffer(420). A controller(440) compares a previous line time data pattern and a current line time data pattern, and the controller outputs a control signal for controlling a switching operation of the charge sharing switch according to a comparison result.

Abstract translation: 提供数据驱动单元和包括该数据驱动单元的液晶显示器，以通过选择性地从数据驱动器预充电和预排放数据信号来防止液晶显示器的故障。 在数据驱动单元和包括该数据驱动单元的液晶显示器中，电荷共享开关（430）与第一缓冲器（410）的输出端子和第二缓冲器（420）的输出端连接。 控制器（440）比较前一行时间数据模式和当前行时间数据模式，并且控制器根据比较结果输出用于控制电荷共享开关的切换操作的控制信号。

公开(公告)号：KR100901394B1

公开(公告)日：2009-06-05

申请号：KR1020070046914

申请日：2007-05-15

Applicant: 삼성전자주식회사

Inventor： 남장진 ,  김태진

IPC: H04L25/02

CPC classification number: H04L25/0278

Abstract: 데이터 전송 장치는 데이터를 송신하는 송신 칩, 복수개의 수신 칩들 및 한 쌍의 전송 라인들을 포함한다. 복수개의 수신칩들은 송신 칩으로부터 송신되는 데이터를 수신하고 데이터가 수신되는 수신칩에서만 종단 저항을 제공한다. 한 쌍의 전송 라인들은 상기 데이터를 상기 송신 칩으로부터 상기 복수개의 수신칩들로 전달하고 데이지 체인 형태의 구조를 갖는다.

公开(公告)号：KR1020090072117A

公开(公告)日：2009-07-02

申请号：KR1020070140117

申请日：2007-12-28

Applicant: 삼성전자주식회사

Inventor： 김태진 ,  남장진

IPC: H03K5/131

CPC classification number: H03K5/135 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0337

Abstract: A deskew system for removing a skew between data signals and a clock and circuits for the same are provided to reduce power consumption and a chip area by reducing the number of clocks for data sampling. A first voltage control delay line(110) receives a data signal and generates the delayed data signals of N by delaying the phase of data signal in response to a phase control signal to 90/N unit. The N is the natural number more than 1. A second voltage control delay line(120) receives a clock and generates the delayed clocks of N by delaying the phase of the clock in response to the phase control signal to 90/N unit. A skew correction control unit(140) generates a plurality of skew control signals for correcting the skew between the data signal and the clock based on the delayed clocks of N, the delayed data signals of N, the clock, and the data signals.

Abstract translation: 提供了用于消除数据信号与时钟之间的偏斜的去偏移系统，并且提供了用于其的电路以通过减少用于数据采样的时钟数来降低功耗和芯片面积。 第一电压控制延迟线（110）通过将相位控制信号响应于90 / N单位延迟数据信号的相位来接收数据信号并产生N的延迟数据信号。 N是大于1的自然数。第二电压控制延迟线（120）通过响应于相位控制信号延迟到90 / N单元来延迟时钟的相位来接收时钟并产生N的延迟时钟。 偏斜校正控制单元（140）根据N的延迟的时钟，N的延迟的数据信号，时钟和数据信号，产生用于校正数据信号与时钟之间的偏差的多个偏斜控制信号。

公开(公告)号：KR1020080100906A

公开(公告)日：2008-11-21

申请号：KR1020070046914

申请日：2007-05-15

Applicant: 삼성전자주식회사

Inventor： 남장진 ,  김태진

IPC: H04L25/02

CPC classification number: H04L25/0278

Abstract: A data transmission device and a method thereof are provided to reduce the number of transmission lines and the area of a PCB by improving an operation speed. A data transmission device comprises the followings: a transmission chip(310) transmitting data; a plurality of receiving chips(340,350,360) which receives the data transmitted from the transmission chip and provides termination resistance; and a pair of transmission lines(330) of a daisy chain type which transmits the data to the receiving chips from the transmission chip. Each receiving chip comprises a pair of input lines(342,352,362) branched from the transmission lines, termination resistance providing units(344,354,364) are connected between the input lines, buffers receiving data from the input lines, and connection switches(348,358,368) connecting the receiving chips with each other.

Abstract translation: 提供了一种数据传输装置及其方法，以通过提高操作速度来减少传输线的数量和PCB的面积。 数据传输装置包括：发送数据的传输芯片（310）; 多个接收芯片（340,350,360），其接收从所述传输芯片发送的数据并提供终端电阻; 以及菊花链型的一对传输线（330），其将数据从传输芯片发送到接收芯片。 每个接收芯片包括从传输线分支的一对输入线（342,352,362），端接电阻提供单元（344,354,364）连接在输入线之间，缓冲器从输入线接收数据，以及连接开关（348,358,368） 与彼此。

公开(公告)号：KR1020080060077A

公开(公告)日：2008-07-01

申请号：KR1020060134173

申请日：2006-12-26

Applicant: 삼성전자주식회사

Inventor： 남장진 ,  서희영

IPC: G02F1/133

CPC classification number: G09G3/3696 ,  G09G3/3688 ,  G09G2320/0223

Abstract: An LCD(Liquid Crystal Display) and an image quality improving method thereof are provided to apply constant power/ground voltage to a source driver regardless of a location of the source driver, thereby reducing a deviation of rising and falling time of an output signal outputted from the source driver. A timing controller(400) generates plural gamma reference voltages by dividing power voltage inputted from a power unit. Regulators(410,420) generate second voltage as output voltage from first voltage as input voltage by using the gamma reference voltages as inner reference voltage. A source driver(430) uses the second voltage as inner bias voltage.

Abstract translation: 提供LCD（液晶显示器）及其图像质量改进方法，以将源电平驱动器的恒定功率/接地电压与源驱动器的位置无关，从而减少输出信号的上升和下降时间的偏差 从源驱动程序。 定时控制器（400）通过分割从功率单元输入的电源电压来产生多个伽马参考电压。 通过使用伽马参考电压作为内部参考电压，调节器（410,420）产生作为来自第一电压的输出电压作为输入电压的第二电压。 源极驱动器（430）使用第二电压作为内部偏置电压。

公开(公告)号：KR100690275B1

公开(公告)日：2007-03-12

申请号：KR1020060009441

申请日：2006-01-31

Applicant: 삼성전자주식회사

Inventor： 남장진 ,  전용원

IPC: G11C29/50

Abstract: A semiconductor integrated circuit is provided to test a chip which operates in a current mode, using an external test device which operates in a voltage mode. A current mode semiconductor integrated circuit operates in a voltage mode in a test mode. The semiconductor integrated circuit includes a first transmission converter(605), a first reception converter(610), and a first output unit(605-2). The first transmission converter receives a first test voltage and converts the first test voltage to a first test current. The first reception converter receives the first test current and a reference current and generates a first output voltage based on the first test current and the reference current. The first output unit outputs the first output voltage to the outside. The semiconductor integrated circuit also includes a test voltage input terminal, which receives the first test voltage, and a current signal input terminal which receives data current and the reference current.

Abstract translation: 提供半导体集成电路以使用以电压模式操作的外部测试装置来测试以电流模式操作的芯片。 电流模式半导体集成电路在测试模式下以电压模式工作。 该半导体集成电路包括第一发送转换器（605），第一接收转换器（610）和第一输出单元（605-2）。 第一传输转换器接收第一测试电压并将第一测试电压转换为第一测试电流。 第一接收转换器接收第一测试电流和参考电流，并且基于第一测试电流和参考电流生成第一输出电压。 第一输出单元将第一输出电压输出到外部。 半导体集成电路还包括接收第一测试电压的测试电压输入端子和接收数据电流和参考电流的电流信号输入端子。

公开(公告)号：KR101448919B1

公开(公告)日：2014-10-13

申请号：KR1020070140117

申请日：2007-12-28

Applicant: 삼성전자주식회사

Inventor： 김태진 ,  남장진

IPC: H03K5/131

CPC classification number: H03K5/135 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0337

Abstract: 디스큐 시스템이 개시된다. 상기 디스큐 시스템은 데이터 신호를 수신하고, 위상 제어 신호에 응답하여 상기 데이터 신호의 위상을 90/N(N은 1이상의 자연수) 단위로 지연시킨 N개의 지연된 데이터 신호들을 발생하며, 상기 데이터 신호와 상기 N개의 지연된 데이터 신호들을 출력하는 제1전압 제어 지연 라인, 클락을 수신하고, 상기 위상 제어 신호에 응답하여 상기 클락의 위상을 90/N 단위로 지연시킨 N개의 지연된 클락들을 발생하며, 상기 클락과 상기 N개의 지연된 클락들을 출력하는 제2전압 제어 지연 라인, 및 상기 데이터 신호, 상기 N개의 지연된 데이터 신호들, 상기 클락, 및 상기 N개의 지연된 클락들에 기초하여 상기 데이터 신호와 상기 클락 사이의 스큐를 보상하기 위한 다수의 스큐 제어 신호들을 발생하는 스큐 보상 제어 유닛를 포함한다.
스큐(skew), 디스큐(deskew)

公开(公告)号：KR1020090080663A

公开(公告)日：2009-07-27

申请号：KR1020080006552

申请日：2008-01-22

Applicant: 삼성전자주식회사

Inventor： 임정필 ,  남장진 ,  김종선

IPC: G09G3/20 ,  G02F1/1345 ,  H05B33/26 ,  G02F1/133

Abstract: A source driver for decreasing the slew rate of output signal and a display device comprising a source driver are provided to reduce the slew rate deviation of data signal according to the location of an plurality of source drivers included in data driver. In a source driver for decreasing the slew rate of output signal and a display device comprising a source driver, an output buffer(143) and a power supply circuits(141, 142) are included the in the source driver. The output buffer is formed as a group composed of a plurality of output buffers outputs data signal. A power voltage supply circuit supplies a plurality of power voltages from the output buffer at the center to the output buffer at the edge.

Abstract translation: 提供用于降低输出信号的转换速率的源极驱动器和包括源极驱动器的显示装置，以根据数据驱动器中包括的多个源极驱动器的位置来减小数据信号的转换速率偏差。 在用于降低输出信号的转换速率的源驱动器和包括源极驱动器的显示装置中，在源极驱动器中包括输出缓冲器（143）和电源电路（141,142）。 输出缓冲器形成为由多个输出缓冲器组成的组输出数据信号。 电源电压电路从中央的输出缓冲器向边缘的输出缓冲器提供多个电源电压。

公开(公告)号：KR100855995B1

公开(公告)日：2008-09-02

申请号：KR1020070050259

申请日：2007-05-23

Applicant: 삼성전자주식회사

Inventor： 남장진 ,  백동훈

IPC: G09G3/20 ,  G02F1/133 ,  G02F1/1345 ,  G09G3/36

CPC classification number: G09G3/3611 ,  G09G2370/08

Abstract: An apparatus and a method for driving a display panel are provided to reduce chip size of a source driver by changing bus configuration between a timing controller and a source driver block. An apparatus for driving a display panel includes a timing controller(220), plural source drivers(250-1,250-2,250-3), first signal transmitters(260-1,-,260-10), and second signal transmitters(270-1,270-2). The timing controller generates signals required for driving a display panel including data and reference signals based on a display drive timing. The source drivers generate signals for driving data lines of the display panel using the signals. The first signal transmitters include buses, which are used for transmitting data between the timing controller and the source drivers, and transmission buses which are used for transmitting the reference signal from the timing controller to one of source drivers. The second signal transmitters include buses which are used for transmitting the reference signal according to a serial cascade connection structure between the source drivers.

Abstract translation: 提供用于驱动显示面板的装置和方法，以通过改变定时控制器和源驱动器块之间的总线配置来减少源驱动器的芯片尺寸。 一种用于驱动显示面板的装置，包括定时控制器（220），多个源极驱动器（250-1,250-2,250-3），第一信号发射器（260-1，...，260-10）和第二信号发射器 1,270-2）。 定时控制器基于显示驱动时序产生驱动显示面板所需的信号，包括数据和参考信号。 源驱动器使用信号产生用于驱动显示面板的数据线的信号。 第一信号发射器包括用于在定时控制器和源极驱动器之间传输数据的总线，以及用于将参考信号从定时控制器发送到源驱动器之一的传输总线。 第二信号发射器包括用于根据源驱动器之间的串联级联连接结构发送参考信号的总线。