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公开(公告)号：KR100082630B1
公开(公告)日：1995-02-22
申请号：KR1019910020914
申请日：1991-11-22
Applicant: 삼성전자주식회사
Inventor： 민경열
IPC: G11C11/407
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公开(公告)号：KR1019940008720B1
公开(公告)日：1994-09-26
申请号：KR1019910020914
申请日：1991-11-22
Applicant: 삼성전자주식회사
Inventor： 민경열
IPC: G11C11/407
Abstract: The arrangement provides isolation transistor which can isolate memory array blocks sharing bit lines. The arrangement comprises: isolation transistors (5,6,7,8) isolating array blocks (A) and (B) which are adjacent to each other and share a bit line. When the memory cell located at block (A) is selected, isolation transistors (6,8) located at block (B) are turned off and sense amp (3) amplifying the data output from block (A), isolation transistors (5,7) located at block (A) performing sensing operation like the above mentioned.
Abstract translation: 该装置提供隔离晶体管，其可隔离共享位线的存储器阵列块。 该布置包括：隔离晶体管（5,6,7,8），隔离彼此相邻并共享位线的阵列块（A）和（B）。 当选择位于块（A）的存储单元时，位于块（B）的隔离晶体管（6,8）被截止，并且读出放大器（3）放大从块（A）输出的数据，隔离晶体管（5， 7）位于块（A），执行如上所述的感测操作。
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公开(公告)号：KR1019930008310B1
公开(公告)日：1993-08-27
申请号：KR1019910001964
申请日：1991-02-05
Applicant: 삼성전자주식회사
IPC: G11C11/40
CPC classification number: G11C8/14
Abstract: The method is for memory array construction in high density memory device fabrication. When the number of strapping word lines between word line decoder and memory array increases, larger size of layout is needed and causes bad effects according to the word line extention. The method comprises: a word line driver unit divided at least 3 times and a word line from one word line driver connected the other line's neighbor line. As a practical example, a memory unit (100) which has four memory array block consists of a column decoder (300) and five allocated word line driver units and a row decoder (60). In this example, the word line driver units are divided by 5. As like it, minimum division number should be over 3.
Abstract translation: 该方法用于高密度存储器件制造中的存储器阵列构造。 当字线解码器和存储器阵列之间的捆扎字线数量增加时，需要更大的布局尺寸，并根据字线延伸产生不良影响。 该方法包括：至少划分3次的字线驱动器单元和连接另一行的相邻行的一个字线驱动器的字线。 作为实例，具有四个存储器阵列块的存储器单元（100）由列解码器（300）和五个分配的字线驱动器单元和行解码器（60）组成。 在这个例子中，字线驱动单位除以5，如最小分割数应该超过3。
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公开(公告)号：KR1019950009234B1
公开(公告)日：1995-08-18
申请号：KR1019920002486
申请日：1992-02-19
Applicant: 삼성전자주식회사
IPC: G11C11/407
Abstract: The generator for generating the clock which isolates the bit lines between adjacent memory cell arrays at semiconductor memory device, comprises: a first memory cell array and a second memory cell array adjacent to the first memory cell array; a pair of first bit lines connected to the first memory cell array and a pair of second bit lines connected to the second memory cell array; an equalizing circuit for equalizing a pair of the first bit lines and a pair of second bit lines; a first separation gate connected between the first memory cell array and a pair of first bit lines; a second separation gate connected between the second memory cell array and a pair of second bit lines; and a means for receiving a high voltage from the exterior, and selectively supplying the received high voltage as a control signals of the first and second separation gates according to a control of a block selection signal.
Abstract translation: 用于产生隔离半导体存储器件的相邻存储单元阵列之间的位线的时钟的发生器包括：与第一存储单元阵列相邻的第一存储单元阵列和第二存储单元阵列; 连接到第一存储单元阵列的一对第一位线和连接到第二存储单元阵列的一对第二位线; 用于均衡一对第一位线和一对第二位线的均衡电路; 连接在第一存储单元阵列与一对第一位线之间的第一分离栅极; 连接在第二存储单元阵列与一对第二位线之间的第二分隔栅极; 以及用于从外部接收高电压的装置，并且根据块选择信号的控制选择性地将所接收的高电压提供为第一和第二分离门的控制信号。
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Patent Agency Ranking
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公开(公告)号：KR100092173B1
公开(公告)日：1995-11-28
申请号：KR1019920002486
申请日：1992-02-19
Applicant: 삼성전자주식회사
IPC: G11C11/407
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公开(公告)号：KR1019930018582A
公开(公告)日：1993-09-22
申请号：KR1019920002486
申请日：1992-02-19
Applicant: 삼성전자주식회사
IPC: G11C11/407
Abstract: 본 발명은 저전원전압을 사용하여 이웃하는 비트라인 사이를 분리시키는 분리게이트를 가지는 반도체 메모리장치에 있어서, 외부로부터 고전압을 입력하여 상기 분리게이트로 상기 전원전압보다 최소한 상기 분리게이트의 드레쉬홀드 전압이상으로 높은 전압을 공급하는 수단을 구비하는 효율적인 데이타 라이트 동작을 실현시킨다.
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公开(公告)号：KR1019940006080B1
公开(公告)日：1994-07-06
申请号：KR1019910013274
申请日：1991-07-31
Applicant: 삼성전자주식회사
Inventor： 민경열
IPC: G11C11/40
Abstract: The circuit consists of some memory cells, wordlines for pointing a row of memory cells, bit lines of pointing a column of memory cells, wordline driver, and sense AMP. The circuit is arranged as follows: wordline driver is divided and arranged four times in one memory cell array at least. One wordline driver is connected with one wordline, the neighboring wordline driver is connected with the other word line. Bit lines make blocks horizontally. A sense amp is located between blocks. One bit line is connected with only one sense amp.
Abstract translation: 该电路由一些存储器单元，用于指向一行存储器单元的字线，指向一列存储器单元的位线，字线驱动器和读出AMP组成。 电路布置如下：字线驱动器至少在一个存储单元阵列中分四次排列。 一个字线驱动器与一个字线连接，相邻字线驱动器与另一个字线连接。 位线使块水平。 感测放大器位于块之间。 一个位线仅与一个读出放大器连接。
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