Abstract:
반도체 장치는 반도체 칩, 보호막 패턴, UBM(Under Bump Metallurgy)막 및 도전성 범프를 포함한다. 반도체 칩은 패드와 가드링(guard ring)을 갖는다. 보호막 패턴은 상기 패드와 상기 가드링이 노출되도록 상기 반도체 칩 상에 형성된다. UBM막은 상기 보호막 패턴 상에 형성되어, 상기 패드 및 상기 가드링과 직접적으로 접촉한다. 도전성 범프는 상기 패드 상에 위치한 상기 UBM막 부분 상에 형성된다. UBM막과 가드링이 직접 접촉하게 되므로, UBM막의 두께 차이에 상관없이 패드들 상에 위치한 UBM막 부분들로 균일한 전류를 공급할 수가 있게 된다.
Abstract:
A semiconductor device, a flip chip package including the same, and a manufacturing method thereof are provided to form conductive bumps with a uniform size by supplying uniform current to all UBM(Under Bump Metallurgy) layers regardless of the thickness difference of the UBM layer. A semiconductor chip(110) includes a pad and a guard ring. A protective pattern(130) is formed on the semiconductor chip and exposes the pad and the guard ring(124). The UBM layer(140) is formed on the protective pattern and contacts the guard ring and the pad directly. A conductive bump(150) is formed in a part of the UBM layer positioned on the pad. The semiconductor chip has an insulating layer pattern(116). The insulating layer pattern includes a trench(118) formed along the circumference of the pad.
Abstract:
A semiconductor device and a manufacturing method thereof are provided to reduce the etching consume rate of the element isolation film side corresponding to the residual amount of the second space pattern in the common contact hole formation. A semiconductor device comprises the element isolation film(102), the gate insulating layer(104), the gate electrode(105a), the first spacer(106a) and the second spacer(107b), the source/drain regions(103a, 103b), and the stress liner film. The element isolation film limits the active area(101) to the semiconductor substrate(100). The gate insulating layer is located on the active area. The gate electrode is located on surface the gate insulating layer. The first spacer is positioned in the gate electrode side wall. The second spacer has the upper side lower than the first spacer. The source/drain region is positioned in the active area of the gate electrode both side. The stress liner film covers the gate electrode and the first and the second spacer.
Abstract:
A MIM(Metal-Insulator-Metal) capacitor and a fabricating method thereof are provided to increase an area of a dielectric pattern and a capacitance of the MIM capacitor by surrounding a top face and a lateral face of a bottom electrode by the dielectric pattern and a top electrode. A bottom electrode(120) of a capacitor is formed on a first interlayer dielectric(110). A dielectric pattern(150) is used for surrounding a top face and a lateral face of the bottom electrode of the capacitor. A top electrode(160) of the capacitor is used for surrounding the dielectric pattern. A second interlayer dielectric(140) is formed on the first interlayer dielectric. The bottom electrode of the capacitor, the dielectric pattern, and the top electrode of the capacitor are formed within an opening(142) of the second interlayer dielectric.
Abstract:
비휘발성 메모리의 소거 방법이 제공된다. 비휘발성 메모리의 소거 방법은 기판에 접지 전압보다 큰 양의 전압을 인가하고, 드레인에 기판에 인가되는 전압보다 크거나 같은 전압을 인가하고, 소오스에 기판에 인가되는 전압보다 큰 전압을 인가하고, 게이트에 접지 전압보다 작은 음의 전압을 인가하여 핫 홀 주입 방법에 의해 소거를 실시한다. 핫 홀 주입, 비휘발성 메모리
Abstract:
금속-절연체-금속 커패시터를 갖는 반도체 소자의 제조방법을 개시한다. 본 발명은 비아 형성을 위한 텅스텐 CMP 전에 커패시터 유전막 CMP를 먼저 실시하여 텅스텐 CMP 시간을 단축시킴으로써, 텅스텐막에 응력이 누적되는 것을 억제하여 크랙 발생을 방지함으로써 커패시터의 불량을 감소시키는 것이다.
Abstract:
A portable terminal and an illegal device mobile identity change prevention method thereof are provided to prevent an illegal device mobile identity change from being attempted, and to change a device mobile identity if a legal change of a device mobile identity is attempted. In case of a device mobile identity change request, new authentication information is received and stored, and the authentication information is encoded to generate encoded authentication information(S202-S212). It is decided whether the first prestored authentication information exists(S214). If not, a device mobile identity is stored, and the encoded authentication information is stored to generate the first authentication information(S215,S217).