公开(公告)号：KR1020130050874A

公开(公告)日：2013-05-16

申请号：KR1020120108745

申请日：2012-09-28

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 김미정 ,  정연식 ,  정재원 ,  박운익

IPC: B82B1/00 ,  B82B3/00

CPC classification number: C09D5/00 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y40/00 ,  C09D153/00 ,  G03F7/0002 ,  H01L21/0337 ,  Y10T428/24612

Abstract: PURPOSE: A nanostructure of a block copolymer is provided to reduce a pattern resolution to about 10nm or less and to improve line edge roughness of a pattern by controlling a difference between at least two solybility parameters(δ) of block structure units in a predetermined range. CONSTITUTION: A block copolymer nanostructure(20) comprises a self-assembled block copolymer on a substrate(10), and the block copolymer comprises multiple block structure units. A difference of solybility parameters(δ) of at least two of the block structure units is equal to or greater than 5 MPa1/2. The block copolymer has a Flory-Huggins interaction parameter(χ) that is equal to or greater than 0.7. A manufacturing method of the block copolymer nanostructure comprises the following steps: (a) forming a block copolymer thin film on a substrate; (b) performing a solvent annealing process to form a pattern on the thin film; and (c) performing a plasma treatment on the pattern to remove other block structure units than the block structure units that form the pattern, thereby manufacturing a nanostructure.

Abstract translation: 目的：提供嵌段共聚物的纳米结构以将图案分辨率降低到约10nm或更小，并且通过控制在预定范围内的块结构单元的至少两个均匀性参数（δ）之间的差异来改善图案的线边缘粗糙度 。 构成：嵌段共聚物纳米结构（20）在基材（10）上包含自组装嵌段共聚物，嵌段共聚物包含多个嵌段结构单元。 至少两个块结构单元的均匀性参数（δ）的差异等于或大于5MPa1 / 2。 嵌段共聚物具有等于或大于0.7的Flory-Huggins相互作用参数（χ）。 嵌段共聚物纳米结构的制造方法包括以下步骤：（a）在基材上形成嵌段共聚物薄膜; （b）进行溶剂退火处理以在薄膜上形成图案; 和（c）对图案进行等离子体处理以去除除了形成图案的块结构单元之外的其它块结构单元，从而制造纳米结构。

公开(公告)号：KR101996493B1

公开(公告)日：2019-07-04

申请号：KR1020120108745

申请日：2012-09-28

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 김미정 ,  정연식 ,  정재원 ,  박운익

IPC: B82B1/00 ,  B82B3/00

公开(公告)号：KR1020090012580A

公开(公告)日：2009-02-04

申请号：KR1020070076516

申请日：2007-07-30

Applicant: 삼성전자주식회사

Inventor： 신재민 ,  유경창 ,  송윤종 ,  박운익 ,  임동원

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1691

Abstract: A manufacturing method of a phase change memory device is provided to decrease the non-resistance of bottom electrode contact and increase the thermal efficiency. A manufacturing method of a phase change memory device comprises a step for forming a lower part phase change material layer on a semiconductor substrate(100); a step for forming a lower part phase change material pattern(130); a step for forming the upper part phase change material layer; a step for forming the upper part phase change material pattern(140). The semiconductor substrate can have a word line(110) and a laminated diode(125). The lower part phase change material layer contacts with a diode. The lower part phase change material pattern is formed on the diode by etching the lower part phase change material layer. The upper part phase change material layer covers the lower part phase change material pattern.

Abstract translation: 提供了相变存储器件的制造方法，以减小底部电极接触的非电阻并提高热效率。 相变存储器件的制造方法包括在半导体衬底（100）上形成下部相变材料层的步骤; 形成下部相变材料图案的步骤; 形成上部相变材料层的工序; 形成上部相变材料图案的步骤。 半导体衬底可以具有字线（110）和层叠二极管（125）。 下部相变材料层与二极管接触。 通过蚀刻下部相变材料层，在二极管上形成下部相变材料图案。 上部相变材料层覆盖下部相变材料图案。