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公开(公告)号：KR101818506B1
公开(公告)日：2018-01-15
申请号：KR1020110083576
申请日：2011-08-22
Applicant: 삼성전자주식회사
CPC classification number: H01L27/11582 , G11C16/0483
Abstract: 바이어스로딩문제가개선된 3차원반도체메모리장치를개시한다. 이를위해본 발명은, 선택트랜지스터와연결된제1 선택라인패스트랜지스터및 메모리셀과연결된제1 워드라인패스트랜지스터를포함하며, 제1 웰영역을공유하는제1 트랜지스터그룹, 선택트랜지스터와연결된제2 선택라인패스트랜지스터를포함하며, 제2 웰영역을공유하는제2 트랜지스터그룹및 제1 트랜지스터그룹및 제2 트랜지스터그룹을제어하는제어부를포함하고, 제어부는, 독출동작에서, 제1 웰영역에음성의(negative) 제1 전압을인가하고, 제2 웰영역에제1 전압보다큰 제2 전압을인가하는것을특징으로하는 3차원반도체메모리장치를제공한다.
Abstract translation: 公开了一种具有改进的偏置负载的三维半导体存储器件。 为此，本发明提供一种半导体存储器件，包括：共用第一阱区的第一晶体管组;连接到第一晶体管的第二晶体管; 包括线传输晶体管和第二晶体管群和上述第一个晶体管组，以及用于控制所述第二晶体管组共享的第二阱区，所述控制单元的控制单元，在读取操作中，语音到第一阱区域 将负的第一电压施加到第二阱区，并且将大于第一电压的第二电压施加到第二阱区。
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公开(公告)号：KR1020060121540A
公开(公告)日：2006-11-29
申请号：KR1020050043779
申请日：2005-05-24
Applicant: 삼성전자주식회사
IPC: G11B20/04
CPC classification number: G06F13/385
Abstract: A memory card for enhancing the reading performance is provided to automatically perform the change of address and command by an accelerator without the intervention of a program. A host interface controller(310) provides an interface related to a host(200) and includes a register set(311). Information such as an address, a command and the like provided from the host and the interrupt information are stored in the register set and initialized whenever the interrupt operation is finished. An MCU(Main Controller Unit)(320) controls the entire operation of a memory card. The MCU fetches an address and a command stored in the register set when the interrupt information is set to the register set.
Abstract translation: 提供了一种用于提高读取性能的存储卡，用于通过加速器自动执行地址和命令的改变而不需要程序干预。 主机接口控制器（310）提供与主机（200）相关的接口并且包括寄存器组（311）。 从主机提供的诸如地址，命令等的信息和中断信息被存储在寄存器组中，并且每当中断操作完成时被初始化。 MCU（主控制器）（320）控制存储卡的整个操作。 当中断信息设置为寄存器集时，MCU将获取存储在寄存器集中的地址和命令。
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公开(公告)号：KR1020060039771A
公开(公告)日：2006-05-09
申请号：KR1020040088988
申请日：2004-11-03
Applicant: 삼성전자주식회사
IPC: G11C16/00
CPC classification number: G11C29/4401 , G06F11/1048 , G11C29/42 , G11C29/76 , G11C2029/0411 , G06F11/1068
Abstract: The data processing method involves determining whether there is a data error in data read from a selected memory block and handling the error differently depending on whether the selected memory block belongs to a code data region or a user data region.
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公开(公告)号：KR100436268B1
公开(公告)日：2004-06-16
申请号：KR1020020026240
申请日：2002-05-13
Applicant: 삼성전자주식회사
Inventor： 박종열
IPC: F24C7/02
CPC classification number: H05B6/6402
Abstract: A microwave oven having an improved configuration of its mounting bracket (80) to couple a magnetron (60) to a waveguide (70), to reduce the number of operations to couple the magnetron to a waveguide, and which is stable in a fixed state of the mounting bracket to obtain a more efficient cooling effect for the magnetron. The microwave oven includes an oven body having a cooking chamber (40) therein and an electric component chamber (50). A mounting bracket (80) is attached to the electric component chamber. The mounting bracket (80) is provided with one or more pockets (86) and is provided near the pocket with a reinforcing section (88) to prevent bending deformation of the mounting bracket. The magnetron (60) is mounted on the mounting bracket, such that has one or more coupling portions (65) are inserted into the corresponding one or more pockets (86) of the mounting bracket (80).
Abstract translation: 一种具有改进其安装托架（80）的配置以将磁控管（60）耦合到波导（70）的微波炉，减少了将磁控管耦合到波导的操作的次数，并且该微波炉在固定状态 以获得对磁控管更有效的冷却效果。 微波炉包括其中具有烹饪室（40）的炉体和电气元件室（50）。 安装托架（80）连接到电气元件室。 安装托架（80）设置有一个或多个凹穴（86），并且在凹穴附近设置有加固部分（88）以防止安装托架弯曲变形。 磁控管（60）安装在安装支架上，使得具有一个或多个耦合部分（65）被插入到安装支架（80）的对应的一个或多个凹穴（86）中。
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公开(公告)号：KR1020100049809A
公开(公告)日：2010-05-13
申请号：KR1020080108804
申请日：2008-11-04
Applicant: 삼성전자주식회사
CPC classification number: G11C16/16 , G11C16/344
Abstract: PURPOSE: An erasing method of a non-volatile memory device is provided to reduce the time of an erasing process by selectively erasing a plurality of memory blocks at the same time. CONSTITUTION: A plurality of memory blocks are erased at the same time using a multi erase voltage(S100). The erase voltage increases using enhancement mode step pulses. One or more failed memory blocks are erased among the memory blocks(S200). The failed information about the memory blocks is provided to a memory control device of the non-volatile memory device.
Abstract translation: 目的：提供一种非易失性存储器件的擦除方法，以通过同时选择性地擦除多个存储器块来减少擦除处理的时间。 构成：使用多次擦除电压同时擦除多个存储块（S100）。 擦除电压使用增强模式步进脉冲增加。 在存储器块中擦除一个或多个失败的存储器块（S200）。 关于存储器块的失败信息被提供给非易失性存储器件的存储器控制器件。
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Patent Agency Ranking
公开(公告)号：KR1020100004791A
公开(公告)日：2010-01-13
申请号：KR1020080065141
申请日：2008-07-04
Applicant: 삼성전자주식회사
Inventor： 박종열
CPC classification number: G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3418 , G11C16/3454
Abstract: PURPOSE: A nonvolatile memory device and a program method thereof are provided to prevent a program disturb phenomenon by increasing a voltage variation width of a word line of the program prohibition cells by double coupling effect between adjacent word lines. CONSTITUTION: A memory cell array block(210) includes a cell string in which a plurality of serially connected memory cells are connected to a bit line. A word line driver(220) drives odd word lines with a first voltage after driving even word lines with the first voltage. The word line driver drops the voltage level of the even word line to the voltage level lower than the first voltage.
Abstract translation: 目的：提供一种非易失性存储器件及其编程方法，以通过在相邻字线之间的双重耦合效应来增加程序禁止单元的字线的电压变化宽度来防止编程干扰现象。 构成：存储单元阵列块（210）包括其中多个串联的存储单元连接到位线的单元串。 在用第一电压驱动偶数字线之后，字线驱动器（220）以第一电压驱动奇数字线。 字线驱动器将偶数字线的电压电平降低到低于第一电压的电压电平。
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公开(公告)号：KR100645058B1
公开(公告)日：2006-11-10
申请号：KR1020040088988
申请日：2004-11-03
Applicant: 삼성전자주식회사
IPC: G11C16/00
CPC classification number: G11C29/4401 , G06F11/1048 , G11C29/42 , G11C29/76 , G11C2029/0411
Abstract: 복수의 메모리 블록들을 갖는 불 휘발성 메모리에 저장된 데이터를 관리하는 방법이 개시되어 있다. 먼저, 선택된 메모리 블록에서 읽혀진 데이터에 에러가 발생하였는 지의 여부가 판별된다. 상기 선택된 메모리 블록에서 읽혀진 데이터에 에러가 발생한 경우, 상기 선택된 메모리 블록이 어느 데이터 영역에 속하는 지의 여부가 판별된다. 상기 선택된 메모리 블록이 코드 데이터 영역인 경우, 상기 읽혀진 데이터의 에러 비트 수가 허용되는 에러 비트 수와 일치하는 지의 여부가 판별된다. 상기 읽혀진 데이터의 에러 비트 수가 허용되는 에러 비트 수와 일치하는 경우, 상기 코드 데이터 영역의 선택된 메모리 블록이 여분의 메모리 블록으로 대체되고 상기 코드 데이터 영역의 선택된 메모리 블록이 사용자 데이터 영역으로 지정된다.
Abstract translation: 公开了一种用于管理存储在具有多个存储块的非易失性存储器中的数据的方法。 首先，确定从所选存储器块读取的数据中是否发生了错误。 如果在从所选择的存储块读取的数据中出现错误，是属于一个数据区域被选择的存储块是否被确定。 如果所选择的存储块是一个代码的数据区，错误是否以匹配被允许在所读取的数据的位错误的数量确定的位的数目。 如果找到一个匹配和比特错误的数量允许在所读取的数据的位错误的数目，码数据区的选定的存储块是由冗余存储块替换被选择时，数据代码区的存储块中的用户数据区被指定。
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公开(公告)号：KR100408402B1
公开(公告)日：2003-12-06
申请号：KR1020010016016
申请日：2001-03-27
Applicant: 삼성전자주식회사
IPC: G11C11/407
CPC classification number: G11C11/406
Abstract: A refresh method for a semiconductor memory device capable of reducing memory cell access time and performing refresh operation is provided. In the refresh method for a semiconductor memory device, when refresh operation is requested, the low address for the refresh operation is latched, and it is determined whether a normal operation command is inputted into the semiconductor memory device. If the normal operation command is inputted into the device, block selection bits of a low address for normal operation is compared with block selection bits of the latched low address for the refresh operation. When block selection bits of both low addresses are the same, a word line for the refresh operation is activated by decoding the latched low address for the refresh operation. A word line for the normal operation is activated by simultaneously decoding the low address for the normal operation while the latched low address for refresh operation is decoded. That is, the normal operation and the refresh operation are simultaneously performed.
Abstract translation: 提供了一种能够减少存储单元访问时间并执行刷新操作的半导体存储器件的刷新方法。 在用于半导体存储器件的刷新方法中，当请求刷新操作时，刷新操作的低地址被锁存，并且确定是否将正常操作命令输入到半导体存储器件中。 如果正常操作命令输入到设备中，则将用于正常操作的低地址的块选择位与用于刷新操作的锁存的低地址的块选择位进行比较。 当两个低地址的块选择位相同时，通过对刷新操作的锁存的低地址进行解码来激活用于刷新操作的字线。 正常操作的字线通过同时解码用于正常操作的低地址而被激活，而用于刷新操作的锁存的低地址被解码。 即，正常操作和刷新操作被同时执行。
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公开(公告)号：KR1020030088580A
公开(公告)日：2003-11-20
申请号：KR1020020026240
申请日：2002-05-13
Applicant: 삼성전자주식회사
Inventor： 박종열
IPC: F24C7/02
CPC classification number: H05B6/6402
Abstract: PURPOSE: A microwave oven is provided to reduce assembly procedures and achieve improved productivity, while permitting the fixing bracket to support the magnetron in a stable manner. CONSTITUTION: A microwave oven comprises a main body; an inner case(30) arranged in the main body in such a manner that the inner space of the inner case forms a cavity and the outer space of the inner case forms an electrical component chamber; and a magnetron(60) fixed to the electrical component chamber, and which supplies a high frequency to the cavity. The magnetron has an upper coupling portion(64) and a lower coupling portion(65), and the fixing bracket has one or more pockets(86) for insertion of the lower coupling portions. The fixing bracket has a reinforcement portion(88) for preventing a warpage of the fixing bracket.
Abstract translation: 目的：提供微波炉以减少组装过程并提高生产率，同时允许固定支架以稳定的方式支撑磁控管。 构成：微波炉包括主体; 内壳体（30），其以使得内壳体的内部空间形成空腔并且内壳体的外部空间形成电气部件室的方式布置在主体中; 以及固定到电气部件室的磁控管（60），并且向空腔提供高频率。 磁控管具有上连接部分（64）和下联接部分（65），并且固定支架具有用于插入下连接部分的一个或多个凹穴（86）。 固定支架具有用于防止固定支架翘曲的加强部分（88）。
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公开(公告)号：KR100372249B1
公开(公告)日：2003-02-19
申请号：KR1020000066347
申请日：2000-11-09
Applicant: 삼성전자주식회사
IPC: G11C11/4063
CPC classification number: G11C11/4085 , G11C11/406
Abstract: Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits with the block control signals.
Abstract translation: 公开了一种半导体存储器件，包括多个子字线驱动器，多个子字线驱动器在位线的方向上布置在所有存储器单元阵列块上并且分别由两个存储器单元阵列块共享，多个块读出放大器布置在所有存储器单元 阵列块在字线方向上并且分别由两个存储单元阵列块共享，多个电路块分别布置在容纳子字线驱动器和块读出放大器的区域交叉的结合区域处; 所述连接区域包括适于驱动区块读出放大器的一个或多个LA驱动器，适于产生驱动控制信号以控制子字线驱动器的一个或多个PXiD电路，以及 - 一个或多个BSYD电路，适于选择性地使LA驱动器响应 发送块控制信号; 以及多个块控制单元，其适于通过组合列和行块地址解码信号来生成上块和下块控制信号，并同时利用块控制信号来激活两个或更多个BSYD电路。
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