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公开(公告)号：KR102225215B1
公开(公告)日：2021-03-09
申请号：KR1020140154464A
申请日：2014-11-07
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/28 , H01L21/31
CPC classification number: H01L28/40 , H01L24/05 , H01L23/5222 , H01L23/5223 , H01L2224/05012 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05558 , H01L2224/05562 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/13014 , H01L2224/13022 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/14131 , H01L2224/94 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L24/13
Abstract: MIM(Metal-Insulator-Metal) 캐패시터의 형상 및, MIM 캐패시터와 단자 패드 사이의 위치 관계 조절하여, MIM 캐패시터의 신뢰성을 개선할 수 있는 반도체 장치를 제공하는 것이다. 상기 반도체 장치는 기판 상의 층간 절연막, 상기 층간 절연막 내에 배치되고, 상기 기판 상에 순차적으로 적층된 제1 하부 전극과, 제1 캐패시터 절연막과, 제1 상부 전극을 포함하는 제1 캐패시터 구조체, 및 상기 층간 절연막 상에 배치되는 단자 패드를 포함하는 금속 배선으로, 상기 단자 패드는 상기 제1 캐패시터 구조체와 비오버랩되는 금속 배선을 포함한다.
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公开(公告)号：KR1020130080154A
公开(公告)日：2013-07-12
申请号：KR1020120000923
申请日：2012-01-04
Applicant: 삼성전자주식회사
CPC classification number: H04M1/72522 , B60W50/08 , B60W50/085 , G06F9/44 , H04W88/02
Abstract: PURPOSE: A vehicle driving information display device of a mobile terminal and a method thereof are provided to daily and monthly display a driving history of a vehicle. CONSTITUTION: An input and output unit (110) inputs the driving information of a vehicle. A calculation unit (120) calculates the driving average of the vehicle by the predetermined time through the inputted information. A display unit (150) displays the calculated average. A control unit (130) classifies each of two or more grades including the grade corresponding to the calculated average. The control unit classifies each of two or more grades into a color, a marking method, and a grade indication. [Reference numerals] (110) Input and output unit; (120) Calculation unit; (130) Control unit; (140) Storage unit; (150) Display unit
Abstract translation: 目的：提供一种移动终端的车辆驾驶信息显示装置及其方法，用于每日和每月显示车辆的驾驶历史。 构成：输入和输出单元（110）输入车辆的驾驶信息。 计算单元（120）通过输入的信息计算车辆的行驶平均预定时间。 显示单元（150）显示计算出的平均值。 控制单元（130）对包括对应于所计算的平均值的等级的两个或更多个等级中的每一个进行分类。 控制单元将两个或多个等级中的每一个分类为颜色，标记方法和等级指示。 （附图标记）（110）输入和输出单元; （120）计算单位; （130）控制单元; （140）存储单元; （150）显示单元
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公开(公告)号：KR1020080060071A
公开(公告)日：2008-07-01
申请号：KR1020060134159
申请日：2006-12-26
Applicant: 삼성전자주식회사
CPC classification number: G03G15/0194 , G03G15/0173 , G03G2215/0132 , G03G2215/0141 , G03G2215/0187
Abstract: An electro-photographic image forming apparatus adopting a transparent toner and a white toner is provided to improve and uniformize a degree of gloss and prevent background pollution by developing the transparent toner in a part on which a colored toner is developed and developing the white toner in a background part. An electro-photographic image forming apparatus includes the first and second photosensitive bodies(11~15), the first and second exposers(31~35), and the first and second developing machines(21~25). The first and second exposers form electrostatic latent images on the first and second photosensitive bodies charged as uniform potential. The first developing machines supply a colored toner to the electrostatic latent images of the first photosensitive bodies and develop the colored toner. The second developing machine contains a transparent toner and a white toner charged as indifferent polarity, supplies the transparent toner and the white toner to an image part and a non-image part of the electrostatic latent image of the second photosensitive body, and develops the transparent toner and the white toner. A pre-transfer charger charges the transparent toner and the white toner developed on the second photosensitive body as the same polarity.
Abstract translation: 提供采用透明调色剂和白色调色剂的电子照相图像形成装置，以改善和均匀化光泽度，并通过在其上显影有色调色剂的部分中显影透明调色剂并显影白色调色剂来防止背景污染 背景部分。 电照相成像设备包括第一和第二感光体（11〜15），第一和第二曝光器（31〜35）以及第一和第二显影机（21〜25）。 第一和第二曝光器在充电为均匀电位的第一和第二感光体上形成静电潜像。 第一显影机向第一感光体的静电潜像供应彩色调色剂并显影着色调色剂。 第二显影机包含透明调色剂和作为无差异极性的白色调色剂，将透明调色剂和白色调色剂供应到第二感光体的静电潜像的图像部分和非图像部分，并显影出透明调色剂 墨粉和白色墨粉。 预转印充电器对透明调色剂和在第二感光体上显影的白色调色剂以相同的极性进行充电。
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公开(公告)号：KR1020030001088A
公开(公告)日：2003-01-06
申请号：KR1020010037420
申请日：2001-06-28
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247 , H01L29/788
CPC classification number: H01L27/11568 , H01L27/105 , H01L27/11573
Abstract: PURPOSE: A non-volatile memory device and a method for fabricating the same are provided to minimize the influence of trap assisted tunneling by improving a structure of non-volatile memory device. CONSTITUTION: An isolation layer(101) is formed on a predetermined region of a semiconductor substrate(100) in order to define the first active regions(103) of a cell array region(a) and the second active regions of a peripheral circuit region(b). A plurality of word lines(140) are arrayed on the first active regions(103) of the cell array region(a) and across an upper portion of the isolation layer(101). A stacked insulating layer is inserted between the word lines(140) and the first active regions(103). The stacked insulating layer is formed with a tunnel oxide layer(152), a charge storage layer(154), and a blocking insulating layer(156). A gate capping oxide layer(142) is inserted between the word lines(140) and the first sidewall spacer(146). The charge storage layer(154) and the blocking insulating layer(156) have projection portions(151). A dopant diffusion layer(150) is formed on the first active region(103) between the word lines(140). A gate electrode(240) is formed on the peripheral circuit region(b). A gate capping oxide layer(142) is inserted between the first sidewall spacer(146) and the gate electrode(240). A plurality of dopant diffusion layers(254) are formed on the second active region(203) of both sides of gate electrode(240). A dopant diffusion layers(254) includes the second and the third dopant diffusion layers(250,252).
Abstract translation: 目的：提供非易失性存储器件及其制造方法，以通过改进非易失性存储器件的结构来最小化陷阱辅助隧穿的影响。 构成：在半导体衬底（100）的预定区域上形成隔离层（101），以便限定电池阵列区域（a）的第一有源区域（103）和外围电路区域的第二有源区域 （b）中。 多个字线（140）被排列在单元阵列区域（a）的第一有源区域（103）上并跨越隔离层（101）的上部。 堆叠的绝缘层插入在字线（140）和第一有源区（103）之间。 层叠绝缘层形成有隧道氧化物层（152），电荷存储层（154）和阻挡绝缘层（156）。 栅极覆盖氧化物层（142）插入在字线（140）和第一侧壁间隔物（146）之间。 电荷存储层（154）和阻挡绝缘层（156）具有突出部分（151）。 在字线（140）之间的第一有源区（103）上形成掺杂剂扩散层（150）。 在外围电路区（b）上形成栅电极（240）。 栅极覆盖氧化物层（142）插入在第一侧壁间隔物（146）和栅电极（240）之间。 在栅电极（240）的两侧的第二有源区（203）上形成多个掺杂剂扩散层（254）。 掺杂剂扩散层（254）包括第二和第三掺杂剂扩散层（250,252）。
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公开(公告)号：KR1020010077518A
公开(公告)日：2001-08-20
申请号：KR1020000005358
申请日：2000-02-03
Applicant: 삼성전자주식회사
IPC: H01L21/82
CPC classification number: H01L27/10855 , H01L21/76831 , H01L21/76897 , H01L27/10885
Abstract: PURPOSE: A method for forming a self-aligned contact structure of a semiconductor integrated circuit is provided to increase a margin for misaligning and prevent line patterns from exposing by extending a narrow contact hole with a wet-etching. CONSTITUTION: A plurality of line patterns(22) are formed on a substrate(1). A capping insulating layer(24) is formed to cover the surface of the line patterns(22) and the surface of the substrate(1). An upper interlayer insulating layer(26a) is formed on the capping insulating layer(24) to fill a gap region between the line patterns(22). The upper interlayer insulating layer(26a) and the capping insulating layer(24) are patterned, so that the first contact hole is formed between the line patterns(22). By wet-etching the upper interlayer insulating layer(26a) selectively, the first contact hole is extended, so that the second contact hole for exposing the capping insulating layer(24) on the sidewall of the line patterns(22) is formed.
Abstract translation: 目的：提供一种用于形成半导体集成电路的自对准接触结构的方法，以增加不对准的余量，并且通过用湿法蚀刻延伸窄的接触孔来防止线图案暴露。 构成：在基板（1）上形成多个线图案（22）。 形成封盖绝缘层（24）以覆盖线图案（22）的表面和基板（1）的表面。 在封盖绝缘层（24）上形成上层间绝缘层（26a）以填充线图案（22）之间的间隙区域。 图案化上层间绝缘层（26a）和封盖绝缘层（24），使得第一接触孔形成在线图案（22）之间。 通过选择性地对上部层间绝缘层（26a）进行湿法蚀刻，第一接触孔延伸，从而形成用于使覆盖绝缘层（24）暴露在线图案（22）的侧壁上的第二接触孔。
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Patent Agency Ranking
公开(公告)号：KR1020000074605A
公开(公告)日：2000-12-15
申请号：KR1019990018655
申请日：1999-05-24
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to guarantee an enough etch margin, by forming an insulating layer for a silicide blocking layer(SBL) with a stacked structure of an oxidation layer and a nitride layer, so as to use a difference of etch rates between the oxidation and nitride layers. CONSTITUTION: A gate electrode(104) is formed on a semiconductor substrate(100). A spacer(106) of a nitride layer is formed on both sidewalls of the gate electrode. A source/drain active region is formed in the substrate on both edges of the gate electrode. An insulating layer for a silicide blocking layer(SBL) composed of an oxidation layer(108) and a nitride layer(110) having different etch selectivity is formed on the resultant structure. A sufficient thickness of the nitride layer is etched so that the oxidation layer remains only in an upper part of the gate electrode and the nitride layer remains only in an active region of a dynamic random access memory(DRAM) cell formation portion. The oxidation layer existing in a portion where the nitride layer does not exist is eliminated. A silicide layer(112) is formed on the gate electrode in the exposed DRAM cell formation portion, the gate electrode in a logic formation portion and the active region.
Abstract translation: 目的：提供一种用于制造半导体器件的方法以通过形成具有氧化层和氮化物层的堆叠结构的硅化物阻挡层（SBL）的绝缘层来确保足够的蚀刻裕度，以便使用差异 的氧化层和氮化物层之间的蚀刻速率。 构成：在半导体衬底（100）上形成栅电极（104）。 氮化物层的间隔物（106）形成在栅电极的两个侧壁上。 在栅电极的两个边缘上的衬底中形成源极/漏极有源区。 在所得结构上形成由氧化层（108）和具有不同蚀刻选择性的氮化物层（110）组成的硅化物阻挡层（SBL）的绝缘层。 蚀刻氮化物层的足够厚度，使得氧化层仅保留在栅电极的上部，并且氮化物层仅保留在动态随机存取存储器（DRAM）单元形成部分的有源区中。 消除了存在于不存在氮化物层的部分中的氧化层。 在暴露的DRAM单元形成部分中的栅电极上形成硅化物层（112），逻辑形成部分中的栅电极和有源区。
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公开(公告)号：KR100263451B1
公开(公告)日：2000-08-01
申请号：KR1019980009137
申请日：1998-03-17
Applicant: 삼성전자주식회사
Inventor： 박종우
IPC: D06F39/12
Abstract: PURPOSE: A washing machine is provided to easily eject the laundry to be finished a washing from a spin basket. CONSTITUTION: A laundry basket(27) is formed by a cylindrical net. A circular pulsator guide passing portion(33) is formed in the lower center of the laundry basket(27) to pass a pulsator guide. A cylindrical safety net(34) is installed in the pulsator guide passing portion(33) to prevent an insertion of the laundry between a pulsator and the pulsator guide passing portion(33) during a washing. Plural hanging hooks(35) are installed on the laundry basket(27) to fix the laundry basket(27) on a spin basket and to separate the lower part of the laundry basket(27) from a pulsator. Plural handles(37) are installed to easily eject the laundry basket(27). Thereby, the laundry to be finished is ejected easily.
Abstract translation: 目的：提供一种洗衣机，以容易地将洗衣机从旋转筐中排出洗涤。 构成：洗衣篮（27）由圆柱形网形成。 在衣物篮（27）的下部中心形成有圆形的波轮引导通过部（33），以使波导引导件通过。 在波轮引导通过部分（33）中安装有圆柱形安全网（34），以防止在洗涤期间衣物在波轮和波轮引导通过部分（33）之间插入。 多个挂钩（35）安装在洗衣篮（27）上，以将洗衣篮（27）固定在旋转筐上并将洗衣篮（27）的下部与波轮分开。 安装多个把手（37）以容易地弹出洗衣篮（27）。 从而容易地喷射要完成的衣物。
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公开(公告)号：KR1020000000885A
公开(公告)日：2000-01-15
申请号：KR1019980020804
申请日：1998-06-05
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L27/10888 , H01L21/76897 , H01L27/10894
Abstract: PURPOSE: A fabrication method is provided to simplify manufacturing processes at the time of a selective solicitation of embedded DRAM merged DRAM and logic without additional photo lithographic and ARL(anti-reflective layer) deposition processes. CONSTITUTION: The method comprises the steps of forming a gate electrode(104) on a silicon substrate(100); forming a spacer(106) at both sidewalls of the gate electrode; forming an active region in the substrate by ion-implanting; forming an insulating layer(110) on the resultant structure; remaining the insulating layer(110) only on the surface of the active region between the gate electrodes by self-aligning method and etching the insulating layer using an etch stopping layer(108) as a mask; and forming a silicide layer(112) on the surface of the gate electrodes and the active regions.
Abstract translation: 目的：提供一种制造方法，以简化在嵌入式DRAM合并的DRAM和逻辑的选择性招募时的制造工艺，而无需额外的光刻和ARL（抗反射层）沉积工艺。 构成：该方法包括在硅衬底（100）上形成栅电极（104）的步骤。 在所述栅电极的两个侧壁处形成间隔物（106）; 通过离子注入在衬底中形成有源区; 在所得结构上形成绝缘层（110）; 仅通过自对准方法在栅电极之间的有源区的表面上剩余绝缘层（110），并使用蚀刻停止层（108）作为掩模蚀刻绝缘层; 以及在栅电极和有源区的表面上形成硅化物层（112）。
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公开(公告)号：KR2019990038025U
公开(公告)日：1999-10-15
申请号：KR2019980003937
申请日：1998-03-17
Applicant: 삼성전자주식회사
Inventor： 박종우
IPC: D06F39/14
Abstract: 본 고안은, 세탁물출입구가 형성된 외부케이싱과, 상기 외부케이싱내에 설치되는 아웃터브와, 상기 외부케이싱의 상기 세탁물출입구를 회동개폐하도록 힌지결합된 도어를 갖는 세탁기에 관한 것으로서, 상기 외부케이싱의 전방측 일부영역에 상면으로부터 하향 함몰된 함몰부가 형성되어 있는 것을 특징으로 한다. 이에 의하여, 세탁물을 용이하게 인출할 수 있는 세탁기가 제공된다.
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公开(公告)号：KR1019990074642A
公开(公告)日：1999-10-05
申请号：KR1019980008357
申请日：1998-03-12
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: 본 발명은 디램소자의 셀 커패시터 형성방법에 관한 것으로, 반도체기판 상에 층간절연막을 형성하고, 층간절연막을 패터닝하여 반도체기판의 소정영역을 노출시키는 제1 매몰콘택홀을 형성한다. 제1 매몰콘택홀 내에 플러그 패턴을 형성한 다음, 결과물 전면에 식각저지막을 형성한다. 식각저지막을 패터닝하여 플러그 패턴의 상부직경보다 작은 직경을 갖고 플러그 패턴의 소정영역을 노출시키는 제2 매몰콘택홀을 형성한다. 계속해서, 제2 매몰콘택홀을 덮는 스토리지 전극을 형성한다. 또한, 제1 매몰콘택홀은 층간절연막 및 제1 식각저지막을 순차적으로 형성한 다음, 제1 식각저지막 및 층간절연막을 연속적으로 패터닝함으로써 형성되어질 수도 있다. 이때, 제1 매몰콘택홀을 채우는 플러그 패턴을 형성하고, 그 결과물 전면에 제2 식각저지막을 형성한다. 그리고, 제2 식각저지막을 패터닝하여 플러그 패턴의 소정영역을 노출시키는 제2 매몰콘택홀을 형성한다. 이어서, 제2 매몰콘택홀을 덮는 스토리지 전극을 형성한다.
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