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公开(公告)号：KR1020160058306A
公开(公告)日：2016-05-25
申请号：KR1020140158824
申请日：2014-11-14
Applicant: 삼성전자주식회사
IPC: H01L21/027 , G03F1/62
CPC classification number: G03F1/62 , H01L21/0274
Abstract: 본발명은마스크를개시한다. 마스크는마스크기판과, 상기마스크기판상의마스크패턴들과, 상기마스크패턴들외곽의상기마스크기판가장자리상에배치된프레임들과, 상기마스크패턴들로부터이격하여상기프레임들상에배치된펠리클을포함한다. 상기펠리클은나노미터의두께를갖는보호층들을포함할수 있다.
Abstract translation: 本发明公开了一种掩模。 掩模包括掩模基板，掩模基板上的掩模图案，布置在掩模图案的周边的掩模基板的边缘上的框架，以及与掩模图案分离并布置在框架上的防护薄膜组件。 防护薄膜组件可以包括具有几纳米厚度的保护层。
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公开(公告)号：KR1020140079616A
公开(公告)日：2014-06-27
申请号：KR1020120147723
申请日：2012-12-17
Applicant: 삼성전자주식회사
Abstract: Disclosed is an extreme ultra violet (EUV) generation device. The EUV generation device includes a light source which outputs a laser beam, a pulse width compressor which compresses the pulse width of the laser beam, a gas cell which receives the laser beam with compressed pulse width and generates an EUV beam, and a vacuum chamber which stores the pulse width compressor and the gas cell.
Abstract translation: 公开了一种极紫外（EUV）产生装置。 EUV产生装置包括输出激光束的光源，压缩激光束的脉冲宽度的脉冲宽度压缩器，接收压缩脉冲宽度的激光束并产生EUV光束的气室，以及真空室 其存储脉冲宽度压缩机和气室。
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公开(公告)号：KR1020000009429A
公开(公告)日：2000-02-15
申请号：KR1019980029831
申请日：1998-07-24
Applicant: 삼성전자주식회사
Inventor： 박종주
IPC: G06F12/00
Abstract: PURPOSE: A circuit for generating a memory address of a data processing system is to be divided into a plurality of page frame and to have a memory capable of access using a page address and a word address. CONSTITUTION: A circuit for generating a memory address comprises: an address bus (2); a data bus (1); a first register (10) to be connected to the data bus (1), for storing a word address for setting a common use region of each page frame; a second register (20) to be connected to the data bus (1), for storing a first page address of a page frame for using the common use region and a second page address of a page frame for using a region except for the common use region; a multiplexer (30) for responding a certain selecting signal and selectively outputting one between the first and second page addresses; and a comparator (50) for comparing the address inputted from the address bus and the word address stored in the first register (10) and outputting the selecting signal. Thereby, the page frame of the memory is managed effectively.
Abstract translation: 目的：用于产生数据处理系统的存储器地址的电路被分成多个页面帧，并且具有能够使用页面地址和字地址访问的存储器。 构成：用于产生存储器地址的电路包括：地址总线（2）; 数据总线（1）; 要连接到数据总线（1）的第一寄存器（10），用于存储用于设置每个页框的共同使用区域的字地址; 要连接到数据总线（1）的第二寄存器（20），用于存储用于使用共同使用区域的页面帧的第一页地址和用于使用除共同之外的区域的页框的第二页地址 使用区域; 多路复用器（30），用于响应某个选择信号并选择性地在第一和第二寻呼地址之间输出一个; 以及用于比较从地址总线输入的地址和存储在第一寄存器（10）中的字地址并输出选择信号的比较器（50）。 从而有效地管理存储器的页面帧。
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公开(公告)号：KR1019930014031A
公开(公告)日：1993-07-22
申请号：KR1019910023338
申请日：1991-12-18
Applicant: 삼성전자주식회사
Inventor： 박종주
IPC: G06F15/02
Abstract: 본 발명은 데이타 뱅크 집적회로에서 특히 중앙처리장치(CPU)의 기능 제약을 해결하기 위하여 램 소팅을 별도로 수행하는 소팅 컨트롤러에 관한 것으로, 종래에는 데이타 뱅크내에 소팅 컨트롤러가 구비되지 않고 중앙처리장치에 의해서 시스템 (system)이 소정의 기억된 데이타를 소팅하여 이로부터 많은 시간이 필요하게 되고 이때 타이머의 구동을 위한 타임체크가 제약을 받는다는 문제가 발생되는 바, 본 발명에서는 데이타 램에 기억된 소정의 데이타를 소팅할 시에 상기 중앙처리장치의 교신에 따라 독립적으로 소팅동작을 실행하는 소팅 컨트롤러(100)를 구비하므로서, 중앙처리장치의 부담을 줄여주고, 대단위 용량의 데이타를 기억시킬 수 있는 데이타 뱅크 집적회로를 구현할 수 있는 효과가 있다.
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公开(公告)号：KR101850493B1
公开(公告)日：2018-04-20
申请号：KR1020110118648
申请日：2011-11-15
Applicant: 삼성전자주식회사
Abstract: 포토마스크의형성방법이제공된다. 본발명에따른포토마스크의형성방법은전사영역을포함하는기판을준비하는것, 상기기판에다층막및 블랭크막을형성하는것, 상기블랭크막을패터닝하여상기전사영역의상기다층막의일부분을노출시키는개구부들를형성하는것 및상기개구부들에의해노출되는다층막의적어도일부분에펄스레이저를조사하는것을포함할수 있다. 상기펄스레이저는 0.001초보다큰 펄스폭을갖질수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020130073429A
公开(公告)日：2013-07-03
申请号：KR1020110141268
申请日：2011-12-23
Applicant: 삼성전자주식회사
CPC classification number: G02B5/1876 , G02B5/1857
Abstract: PURPOSE: A zone plate is provided to improve the concentration efficiency of the light, and, therefore, to be able to improve the measurement efficiency of a mask pattern measuring device. CONSTITUTION: A zone plate (100) comprises a first pattern (10) consisting of a first material with first thickness; and a second pattern (20) consisting of a second material with second thickness bigger than the first thickness, and formed in adjacent to the first pattern. The incident light which, has come to the first pattern from the outside, penetrates the first pattern consisting of the first material. The incident light which has come to the second pattern penetrates the second pattern consisting of the second material. The first material and the second material include the same light-transmissive material.
Abstract translation: 目的：提供一种区域板，以提高光的浓度效率，因此能够提高掩模图案测量装置的测量效率。 构造：区板（100）包括由具有第一厚度的第一材料组成的第一图案（10） 以及第二图案（20），其由具有大于所述第一厚度的第二厚度的第二材料组成，并且与所述第一图案相邻地形成。 从外部到达第一图案的入射光穿透由第一材料组成的第一图案。 已经到达第二图案的入射光穿透由第二材料组成的第二图案。 第一材料和第二材料包括相同的透光材料。
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公开(公告)号：KR1020130067331A
公开(公告)日：2013-06-24
申请号：KR1020110118648
申请日：2011-11-15
Applicant: 삼성전자주식회사
Abstract: PURPOSE: A formation method of a photomask and a photomask formed thereby are provided to simplify processes for manufacturing the photomask by reducing the widths of patterns to be transferred on a semiconductor substrate. CONSTITUTION: A formation method of a photomask includes the following steps of: preparing a substrate with a transferring area(A); forming a multilayer film(110) and a blank film on the substrate; patterning the blank film; forming openings(125c) through which a part of the multilayer film is exposed; and irradiating a part of the multilayer film with pulse laser. The pulse width of the pulse laser is greater than 0.001 seconds. In the multilayer film, a first thin film and a second thin film are alternately stacked. The thin films have first and second refractive indexes. The second refractive index is smaller than the first refractive index.
Abstract translation: 目的：提供光掩模和由此形成的光掩模的形成方法，以简化通过减小要在半导体衬底上转印的图案的宽度来制造光掩模的工艺。 构成：光掩模的形成方法包括以下步骤：制备具有转印区域（A）的基板; 在基板上形成多层膜（110）和空白膜; 图案化空白膜; 形成所述多层膜的一部分露出的开口部（125c） 并用脉冲激光照射多层膜的一部分。 脉冲激光的脉冲宽度大于0.001秒。 在多层膜中，交替层叠第一薄膜和第二薄膜。 薄膜具有第一和第二折射率。 第二折射率小于第一折射率。
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公开(公告)号：KR1019940005507B1
公开(公告)日：1994-06-20
申请号：KR1019870006319
申请日：1987-06-22
Applicant: 삼성전자주식회사
IPC: H03K19/00
Abstract: The circuit provides a CMOS dynamic logic circuit with a function which prevents unstable operation due to the rise of temperature during low speed operation by reducing the hold time through adjusting of the enable clock. The circuit includes a frequency generator (10) with a clock duty controller (40). The clock duty controller consists of a flipflop (F2) for dividing the clock of the frequency generator, a NOR gate (G2) and a NOT gate (G3) for phase shift of the clock. The duty of the clock changes from 0.5 to 0.75 due to the clock duty controller, and the circuit provides the same effect as increasing frequency by twice.
Abstract translation: 该电路提供了具有功能的CMOS动态逻辑电路，其通过调节使能时钟来减少保持时间，从而防止由于低速操作期间的温度升高而导致的不稳定操作。 电路包括具有时钟占空比控制器（40）的频率发生器（10）。 时钟占空比控制器包括用于分频频率发生器的时钟的触发器（F2），用于时钟相移的NOR门（G2）和NOT门（G3）。 由于时钟占空比控制器，时钟的占空比从0.5变为0.75，并且电路提供与增加频率相同的效果两倍。
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