公开(公告)号：KR1020080046483A

公开(公告)日：2008-05-27

申请号：KR1020060116005

申请日：2006-11-22

Applicant: 삼성전자주식회사

Inventor： 이욱형 ,  박증환 ,  변기열

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/76229 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11536 ,  H01L21/28273

Abstract: A method for fabricating a semiconductor device is provided to make uniform the scattering of the CD(critical dimension) of a cell gate pattern by reducing a loading effect caused by a thickness difference between the center and the edge of a cell region. A semiconductor substrate(100) includes a cell region(A), a peripheral region(C) and a boundary region(B) between the cell region and the peripheral region. Insulation patterns define a cell activation region and a peripheral activation region, having a protrusion part higher than the upper surface of the substrate. First conductive layers are formed on the cell and peripheral activation regions. A first insulation layer is interposed between the cell and peripheral activation regions and the first conductive layers. A first buffer layer is formed on the resultant structure. The buffer layer, the first conductive layers and the first insulation layer in the peripheral region are removed so that isolation patterns(112) having a lower upper surface than that of the isolation patterns in the cell region are formed while the peripheral activation region is exposed. A second insulation layer(118) is formed in the exposed peripheral activation region. A second conductive layer and a second buffer layer are formed on the resultant structure. The second buffer layer and the second conductive layer in the cell region are removed so that the first buffer layer in the cell region is exposed and a second conductive pattern(128a) protruding to the boundary region is formed. The second conductive pattern protruding to the boundary region is selectively etched.

Abstract translation: 提供一种制造半导体器件的方法，通过减小由单元区域的中心和边缘之间的厚度差引起的负载效应，使单元栅极图案的CD（临界尺寸）的散射均匀。 半导体衬底（100）包括在单元区域和周边区域之间的单元区域（A），外围区域（C）和边界区域（B）。 绝缘图形限定了细胞活化区域和周边激活区域，其具有高于基底的上表面的突出部分。 在电池和外围激活区域上形成第一导电层。 第一绝缘层插入在电池和外围激活区域和第一导电层之间。 在所得结构上形成第一缓冲层。 除去周边区域中的缓冲层，第一导电层和第一绝缘层，从而形成具有比单元区域中的隔离图案的上表面更低的隔离图案（112），同时外围激活区域被暴露 。 在暴露的周边激活区域中形成第二绝缘层（118）。 在所得结构上形成第二导电层和第二缓冲层。 去除单元区域中的第二缓冲层和第二导电层，使得单元区域中的第一缓冲层被暴露，并且形成突出到边界区域的第二导电图案（128a）。 突出到边界区域的第二导电图案被选择性地蚀刻。

公开(公告)号：KR1020090034168A

公开(公告)日：2009-04-07

申请号：KR1020070099406

申请日：2007-10-02

Applicant: 삼성전자주식회사

Inventor： 변기열 ,  박찬광 ,  문재환 ,  임태완 ,  김승아

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L21/76232 ,  H01L27/11521 ,  H01L21/0223 ,  H01L21/3213

Abstract: A semiconductor device and manufacturing method thereof are provided to prevent the interference between the neighboring floating gates by forming the oxide pattern different having different etch selectivity through re-oxidation. Provided is the substrate(100) including the first insulating layer and conductive patterns. The first oxide film is formed in the surface of conductive patterns through the oxidation process. The second oxide film is formed between conductive patterns. The recess process is performed on the first oxide film and the second oxide film. The first oxide pattern(146) and the second oxide pattern(156) are formed on the device isolation pattern. The second insulating layer(160) and conductive film(170) are formed on the conductive patterns, the first oxide pattern and the second oxide pattern.

Abstract translation: 提供了一种半导体器件及其制造方法，以通过再氧化形成具有不同蚀刻选择性的不同的氧化物图案来防止相邻浮栅之间的干涉。 提供了包括第一绝缘层和导电图案的基板（100）。 第一氧化膜通过氧化工艺形成在导电图案的表面上。 第二氧化膜形成在导电图案之间。 在第一氧化膜和第二氧化物膜上进行凹陷处理。 第一氧化物图案（146）和第二氧化物图案（156）形成在器件隔离图案上。 在导电图案，第一氧化物图案和第二氧化物图案上形成第二绝缘层（160）和导电膜（170）。

公开(公告)号：KR101386430B1

公开(公告)日：2014-04-21

申请号：KR1020070099406

申请日：2007-10-02

Applicant: 삼성전자주식회사

Inventor： 변기열 ,  박찬광 ,  문재환 ,  임태완 ,  김승아

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L21/76232 ,  H01L27/11521

Abstract: 반도체 소자 및 그 제조방법이 개시된다. 상기 반도체 소자는 가장자리가 곡진 활성 영역을 포함하고, 상기 활성 영역 상의 게이트 절연막, 플로팅 게이트, 게이트 층간 유전막 및 컨트롤 게이트 라인을 포함하며, 서로 이웃한 플로팅 게이트들 사이에 오목한 상부면을 갖는 산화패턴을 포함할 수 있다. 상기 컨트롤 게이트는 상기 산화패턴에 의해 상기 활성 영역으로부터 충분한 거리만큼 이격될 수 있다. 상기 제조방법은 재산화 공정 단계를 포함하여, 곡진 가장자리를 갖는 활성 영역 및 오목한 상부면을 갖는 산화패턴을 포함하는 반도체 소자를 제공할 수 있다.
게이트 절연막, 재산화, 라디칼 산화, 활성 영역

公开(公告)号：KR100825789B1

公开(公告)日：2008-04-28

申请号：KR1020060108527

申请日：2006-11-03

Applicant: 삼성전자주식회사

Inventor： 변기열 ,  이욱형 ,  김재훈

IPC: H01L27/115 ,  B82Y10/00

CPC classification number: H01L27/2436 ,  B82Y10/00 ,  H01L21/28273

Abstract: A non-volatile memory device and a method for manufacturing the same are provided to suppress loss of an active region in an edge of a peripheral region by forming sequentially gate electrodes of a MOS transistor. A cell region and a peripheral region are defined on a semiconductor substrate(105). A memory transistor includes a storage node layer(125a) of the cell region and a control gate electrode of the storage node layer. A MOS transistor includes a first gate electrode(145b) of the peripheral region and a second gate electrode(170a,170b) connected electrically to the first gate electrode. The control gate electrode of the memory transistor and the second gate electrode of the MOS transistor are formed with the same material. The control gate electrode is arranged to surround a sidewall of the storage node layer along a word line direction.

Abstract translation: 提供了一种非易失性存储器件及其制造方法，以通过依次形成MOS晶体管的栅电极来抑制边缘边缘中的有源区的损耗。 在半导体衬底（105）上限定单元区域和周边区域。 存储晶体管包括单元区域的存储节点层（125a）和存储节点层的控制栅电极。 MOS晶体管包括周边区域的第一栅电极（145b）和与第一栅电极电连接的第二栅电极（170a，170b）。 存储晶体管的控制栅电极和MOS晶体管的第二栅电极由相同的材料形成。 控制栅电极被布置成沿着字线方向围绕存储节点层的侧壁。