公开(公告)号：KR3007331370000S

公开(公告)日：2014-03-11

申请号：KR3020120058348

申请日：2012-12-05

Applicant: 삼성전자주식회사

Designer： 이욱형 ,  신동호 ,  박봉희 ,  최재원 ,  권순재 ,  전종구 ,  한미란 ,  서정로

公开(公告)号：KR1020120030818A

公开(公告)日：2012-03-29

申请号：KR1020100092587

申请日：2010-09-20

Applicant: 삼성전자주식회사

Inventor： 이욱형

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/16 ,  G11C16/3404

Abstract: PURPOSE: A nonvolatile memory apparatus and an elimination method thereof are provided to significantly increase a read margin of the nonvolatile memory apparatus by narrowing elimination distribution of memory cells. CONSTITUTION: A plurality of memory cells is simultaneously eliminated(S110). A post-program process is performed by selecting over-erased memory cells. A post-elimination process is performed by selecting memory cells which have high threshold voltage(S120). Positive high voltage is supplied to a bit line of the selected memory cell and negative high voltage is supplied to a word line of the selected memory cell in the post-elimination process.

Abstract translation: 目的：提供一种非易失性存储装置及其消除方法，通过缩小存储单元的消除分布来显着增加非易失性存储装置的读取余量。 构成：同时消除多个存储单元（S110）。 通过选择过度擦除的存储器单元来执行后期程序处理。 通过选择具有高阈值电压的存储单元执行后消除处理（S120）。 正高电压被提供给所选择的存储单元的位线，并且在后消除处理中将负高电压提供给所选存储单元的字线。

公开(公告)号：KR1020080035156A

公开(公告)日：2008-04-23

申请号：KR1020060101442

申请日：2006-10-18

Applicant: 삼성전자주식회사

Inventor： 장채명 ,  심상필 ,  이욱형 ,  한지훈

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823443 ,  H01L21/823418 ,  H01L21/823468

Abstract: A method for fabricating a semiconductor integrated circuit device is provided to avoid a short-circuit of a semiconductor device by forming an L-shaped spacer and by extending a silicide layer toward a gate electrode so that the silicide layer is connected to a gate electrode. A semiconductor substrate(100) is prepared in which a first region, a second region and a third region are defined. A gate insulation layer(110) and a gate electrode(120) are formed on the semiconductor substrate. An L-shaped spacer(140,141) is formed on the lateral surface of the gate electrode in the first to third regions. An ion implantation process for forming a source/drain region(150) is performed on the semiconductor substrate. A silicide process is performed to form a silicide layer on the gate electrode and the source/drain region. First and second etch stop layers(210,220) are conformally formed on the semiconductor substrate. An interlayer dielectric(230) is formed on the second etch stop layer. A contact(232) penetrates the interlayer dielectric, the second and first etch stop layers to be connected to the silicide layer. The first region can designate a cell region, and the second and third regions can designate a core-peri region wherein the second region is a high voltage region and the third region is a low voltage region.

Abstract translation: 提供一种制造半导体集成电路器件的方法，以通过形成L形间隔物并通过将硅化物层延伸到栅电极来避免半导体器件的短路，使得硅化物层连接到栅电极。 制备其中限定了第一区域，第二区域和第三区域的半导体衬底（100）。 在半导体衬底上形成栅绝缘层（110）和栅电极（120）。 在第一至第三区域中的栅电极的侧表面上形成L形间隔物（140,141）。 在半导体衬底上执行用于形成源/漏区（150）的离子注入工艺。 执行硅化处理以在栅极电极和源极/漏极区域上形成硅化物层。 第一和第二蚀刻停止层（210,220）共形地形成在半导体衬底上。 在第二蚀刻停止层上形成层间电介质（230）。 触点（232）穿透层间电介质，第二和第一蚀刻停止层连接到硅化物层。 第一区域可以指定单元区域，第二区域和第三区域可以指定核心周边区域，其中第二区域是高电压区域，第三区域是低电压区域。

公开(公告)号：KR100696382B1

公开(公告)日：2007-03-19

申请号：KR1020050070322

申请日：2005-08-01

Applicant: 삼성전자주식회사

Inventor： 이욱형

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76229 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

Abstract: 본 발명은 트렌치 소자분리막을 갖는 반도체 소자 및 그 제조방법을 제공한다. 이 제조방법은 반도체 기판을 준비하고, 반도체 기판의 주변회로 영역에 복수개의 트렌치를 형성하여 트렌치 내부를 채우는 소자분리막을 형성하는 것을 포함하고, 반도체 기판의 셀 어레이 영역에 복수개의 트렌치를 형성하여 트렌치의 내부를 채우는 소자분리막을 형성한다. 주변회로 영역 및 셀 어레이 영역의 트렌치들은 각각 다른 공정으로 형성된다. 주변회로 영역 및 셀 어레이 영역의 소자분리막은 서로 다른 절연물질로 구성되며, 각각 고밀도 플라즈마 CVD 산화물 및 USG 산화물이다.
셀 어레이, 주변회로, 트렌치, 소자분리, 종횡비, 보이드

Abstract translation: 本发明提供了一种具有沟槽隔离膜的半导体器件及其制造方法。 该制造方法包括：制备半导体衬底，以形成在半导体衬底中的所述外围电路区域中的多个沟槽，并且包括用于填充所述沟槽中形成器件隔离膜，在半导体衬底中的沟槽的单元阵列区中形成多个沟槽的 由此形成元件隔离膜。 单元阵列区域的外围电路区域和沟槽由不同的工艺形成。 外围电路区域和单元阵列区域的器件隔离膜由不同的绝缘材料制成，并且分别是致密等离子体CVD氧化物和USG氧化物。

公开(公告)号：KR100684198B1

公开(公告)日：2007-02-20

申请号：KR1020050086616

申请日：2005-09-16

Applicant: 삼성전자주식회사

Inventor： 이욱형

IPC: H01L21/8247 ,  H01L27/115

公开(公告)号：KR1020040036016A

公开(公告)日：2004-04-30

申请号：KR1020020064768

申请日：2002-10-23

Applicant: 삼성전자주식회사

Inventor： 이욱형

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: PURPOSE: A non-volatile memory device for preventing charge loss of a floating gate and a fabricating method thereof are provided to enhance a gathering effect of movable cations permeated to the floating gate by implanting a gap-fill insulating layer of a trench. CONSTITUTION: A plurality of floating gate lines are formed in parallel on a substrate(2). A trench is formed by etching the substrate(2) between the floating gate lines. A gap-fill insulating layer(12) is formed on the trench and a gap between the floating gate lines. A conductive layer is formed by inserting an inter-gate insulating layer on the floating gate line and the gap-fill insulating layer. A word line and a floating gate aligned to the word line are formed by patterning the conductive layer and the floating gate lines. An impurity is implanted into the hap-fill insulating layer to gather cations.

Abstract translation: 目的：提供一种用于防止浮动栅极的电荷损失的非易失性存储器件及其制造方法，以通过注入沟槽的间隙填充绝缘层来增强透过浮动栅极的可移动阳极的聚集效应。 构成：在基板（2）上平行地形成多个浮栅。 通过蚀刻浮置栅极线之间的衬底（2）形成沟槽。 间隙填充绝缘层（12）形成在沟槽和浮栅之间的间隙。 通过在浮栅和间隙填充绝缘层上插入栅极间绝缘层来形成导电层。 通过对导电层和浮栅线图案化，形成与字线对准的字线和浮栅。 将杂质注入到充电绝缘层中以收集阳离子。

公开(公告)号：KR3008706680000S

公开(公告)日：2016-09-01

申请号：KR3020150037461

申请日：2015-07-24

Applicant: 삼성전자주식회사

Designer： 이욱형 ,  조용선 ,  정동현 ,  장지호 ,  박동규 ,  박해광 ,  오은미 ,  이윤재 ,  임동현 ,  조재연

公开(公告)号：KR1020080046483A

公开(公告)日：2008-05-27

申请号：KR1020060116005

申请日：2006-11-22

Applicant: 삼성전자주식회사

Inventor： 이욱형 ,  박증환 ,  변기열

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/76229 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11536 ,  H01L21/28273

Abstract: A method for fabricating a semiconductor device is provided to make uniform the scattering of the CD(critical dimension) of a cell gate pattern by reducing a loading effect caused by a thickness difference between the center and the edge of a cell region. A semiconductor substrate(100) includes a cell region(A), a peripheral region(C) and a boundary region(B) between the cell region and the peripheral region. Insulation patterns define a cell activation region and a peripheral activation region, having a protrusion part higher than the upper surface of the substrate. First conductive layers are formed on the cell and peripheral activation regions. A first insulation layer is interposed between the cell and peripheral activation regions and the first conductive layers. A first buffer layer is formed on the resultant structure. The buffer layer, the first conductive layers and the first insulation layer in the peripheral region are removed so that isolation patterns(112) having a lower upper surface than that of the isolation patterns in the cell region are formed while the peripheral activation region is exposed. A second insulation layer(118) is formed in the exposed peripheral activation region. A second conductive layer and a second buffer layer are formed on the resultant structure. The second buffer layer and the second conductive layer in the cell region are removed so that the first buffer layer in the cell region is exposed and a second conductive pattern(128a) protruding to the boundary region is formed. The second conductive pattern protruding to the boundary region is selectively etched.

Abstract translation: 提供一种制造半导体器件的方法，通过减小由单元区域的中心和边缘之间的厚度差引起的负载效应，使单元栅极图案的CD（临界尺寸）的散射均匀。 半导体衬底（100）包括在单元区域和周边区域之间的单元区域（A），外围区域（C）和边界区域（B）。 绝缘图形限定了细胞活化区域和周边激活区域，其具有高于基底的上表面的突出部分。 在电池和外围激活区域上形成第一导电层。 第一绝缘层插入在电池和外围激活区域和第一导电层之间。 在所得结构上形成第一缓冲层。 除去周边区域中的缓冲层，第一导电层和第一绝缘层，从而形成具有比单元区域中的隔离图案的上表面更低的隔离图案（112），同时外围激活区域被暴露 。 在暴露的周边激活区域中形成第二绝缘层（118）。 在所得结构上形成第二导电层和第二缓冲层。 去除单元区域中的第二缓冲层和第二导电层，使得单元区域中的第一缓冲层被暴露，并且形成突出到边界区域的第二导电图案（128a）。 突出到边界区域的第二导电图案被选择性地蚀刻。

公开(公告)号：KR1020070005791A

公开(公告)日：2007-01-10

申请号：KR1020050060808

申请日：2005-07-06

Applicant: 삼성전자주식회사

Inventor： 이욱형

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/2436 ,  H01L21/823425 ,  H01L27/2463

Abstract: A non-volatile semiconductor memory device is provided to guarantee a process margin capable of forming a via for connecting a common source line and an interconnection by extending both ends of the common source line in a direction of the interconnection. A common source line(40) is formed on a substrate(10). A plurality of bitlines(30) are formed at both sides of the common source line. A pair of interconnections(50) cross each other at both ends of the common source line. A pair of vias(52) are formed at both ends of the common source line, connecting the common source line to the interconnection. Both the ends of the common source line are extended in the direction of the interconnection. The plurality of bitlines cross one of the pair of interconnections.

Abstract translation: 提供了一种非易失性半导体存储器件，以保证能够形成用于连接公共源极线和互连的通孔的工艺余量，其通过在互连方向上延伸公共源极线的两端。 在基板（10）上形成共同的源极线（40）。 在公共源极线的两侧形成多个位线（30）。 一对互连（50）在公共源极线的两端彼此交叉。 在公共源极线的两端形成一对通孔（52），将公共源极线连接到互连线。 公共源极线的两端在互连方向上延伸。 多个位线穿过该对互连中的一个。

公开(公告)号：KR100585068B1

公开(公告)日：2006-05-30

申请号：KR1019990032909

申请日：1999-08-11

Applicant: 삼성전자주식회사

Inventor： 이욱형

IPC: H01L21/28

Abstract: 본 발명은 반도체 소자에 관한 것으로, 특히 트랜지스터의 게이트의 RC 시간 지연을 최소화할 수 있는 반도체 소자의 콘택홀 형성방법에 관한 것이다. 제1 도전막과 제2 도전막 사이에 층간 절연막을 형성한 구조의 게이트를 갖는 트랜지스터를 형성한다. 채널 영역을 기준으로 양측으로 신장되어 있는 게이트 상에 각각 버팅 콘택홀을 형성한다. 이때, 상기 채널 영역의 폭이 20㎛ 이상일 때 본 발명이 유효하게 이용될 수 있으며, 버팅 콘택홀의 배치 위치가 게이트 중심점에 대해 대칭인 경우 더욱 효과적이다.

Abstract translation: 本发明涉及一种半导体器件，并且更具体地涉及一种在能够使晶体管的栅极的RC时间延迟最小化的半导体器件中形成接触孔的方法。 形成具有在第一导电膜和第二导电膜之间形成有层间绝缘膜的结构的栅极的晶体管。 在沟道区域两侧延伸的栅极上形成对接接触孔。 此时，当沟道区的宽度为20μm或更大时，可以有效地使用本发明，并且当对接接触孔的放置位置相对于栅极中心点对称时更有效。