公开(公告)号：KR101923120B1

公开(公告)日：2018-11-28

申请号：KR1020120028575

申请日：2012-03-21

Applicant: 삼성전자주식회사

Inventor： 김호준 ,  이해왕 ,  박철홍 ,  손동균 ,  윤종식

IPC: H01L21/28

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 인접하는패턴을연결하는각각의컨택사이에형성되는스페이서를사용하여, 스케일러빌러티(scalability)를향상시키는반도체소자를제공하는것이다. 기판상에형성되는층간절연막패턴, 상기층간절연막패턴내에형성되고, 제1 방향으로제1 길이를갖는제1 배선, 상기층간절연막패턴내에상기제1 배선과이격되어형성되고, 상기제1 방향으로상기제1 길이과다른제2 길이를갖는제2 배선, 상기제1 배선및상기제2 배선과접하도록형성되어, 상기제1 배선과상기제2 배선을전기적으로분리시키는스페이서를포함한다.

公开(公告)号：KR1020130106917A

公开(公告)日：2013-10-01

申请号：KR1020120028575

申请日：2012-03-21

Applicant: 삼성전자주식회사

Inventor： 김호준 ,  이해왕 ,  박철홍 ,  손동균 ,  윤종식

IPC: H01L21/28

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve the scalability by using a spacer formed between contacts. CONSTITUTION: An interlayer insulating film pattern (100) is formed on a substrate. A first wiring (200) is formed within the interlayer insulating film pattern and has a first length in a first direction. A second wiring (400) is formed within the interlayer insulating film pattern to be spaced apart from the first wiring and has a second length in the first direction. A spacer (300) is in contact with the first and second wirings. The spacer electrically separates the first wiring and the second wiring.

Abstract translation: 目的：提供半导体器件及其制造方法，以通过使用在触点之间形成的间隔来提高可伸缩性。 构成：在基板上形成层间绝缘膜图案（100）。 第一布线（200）形成在层间绝缘膜图案内，并且在第一方向上具有第一长度。 第二布线（400）形成在层间绝缘膜图案内以与第一布线间隔开，并且在第一方向上具有第二长度。 间隔件（300）与第一和第二布线接触。 间隔件电分离第一布线和第二布线。

公开(公告)号：KR1020110044496A

公开(公告)日：2011-04-29

申请号：KR1020090101204

申请日：2009-10-23

Applicant: 삼성전자주식회사

Inventor： 손동균 ,  강동한 ,  박우찬 ,  강상훈

IPC: G06F3/0488 ,  G06F3/0481 ,  H04B1/40

CPC classification number: G06F3/04883

Abstract: PURPOSE: An input signal processing apparatus of a mobile terminal and method thereof are provided to control repetitive input signal generation and to support input signal generation. CONSTITUTION: An input signal is generated from an input unit or a touch screen. The collected input signal copes with a preset condition input signal. A currently active application program is operated based on the repetitive input signal. A user determines a condition input signal type item. A screen is outputted on a display unit.

Abstract translation: 目的：提供移动终端的输入信号处理装置及其方法，以控制重复的输入信号产生并支持输入信号的产生。 构成：从输入单元或触摸屏产生输入信号。 收集的输入信号处理预置条件输入信号。 基于重复输入信号操作当前活动的应用程序。 用户确定条件输入信号类型项目。 在显示单元上输出画面。

公开(公告)号：KR101908451B1

公开(公告)日：2018-10-16

申请号：KR1020120059923

申请日：2012-06-04

Applicant: 삼성전자주식회사

Inventor： 이수연 ,  심상필 ,  손동균 ,  임세찬

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: 본발명에따른반도체소자는, 실리콘기판상에게이트절연막및 게이트전극을포함하는게이트구조물이구비된다. 상기게이트구조물양 측에는스페이서가구비된다. 상기스페이서양 측의실리콘기판부위에는상기게이트구조물의저면보다높은상부면을갖도록돌출된형상을갖고, 상기돌출된부위에는상기실리콘기판의평탄면에대해각도를갖는파세트를포함하여상기스페이서와의사이에패여진부위가생성되고, 불순물영역이포함되는실리콘게르마늄패턴이구비된다. 상기실리콘게르마늄패턴의파세트및 스페이서사이의패여진부위가유지되면서, 상기실리콘게르마늄패턴및 스페이서표면프로파일을따라블록킹절연막이구비된다. 상기블록킹절연막의일부상부면에구비되고, 상기실리콘게르마늄패턴및 스페이서사이의패여진부위를채우는형상을갖는절연윙 패턴이구비된다.

公开(公告)号：KR1020130136250A

公开(公告)日：2013-12-12

申请号：KR1020120059923

申请日：2012-06-04

Applicant: 삼성전자주식회사

Inventor： 이수연 ,  심상필 ,  손동균 ,  임세찬

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device according to the present invention has a gate structure including a gate insulating film and a gate electrode on a silicon substrate. The gate structure is equipped with spacers on both sides. The silicon substrate areas of both sides of the spacer have silicon germanium patterns which have: a protruding shape in order to have a top surface which is higher than the bottom surface of the gate structure; a furrowed part between the protruding part and the spacer by including a fossette having an angle about the flat surface of the silicon; and an impurity area. A blocking insulating film is arranged along the profile of the silicon germanium pattern and the spacer surface while maintaining the furrowed part between the fossette of the silicon germanium pattern and the spacer. An insulating wing pattern is mounted in the form of being arranged on the upper partial surface of the blocking insulating film and filling the furrowed part between the silicon germanium pattern and the spacer.

Abstract translation: 根据本发明的半导体器件具有在硅衬底上包括栅绝缘膜和栅电极的栅极结构。 门结构在两侧配有间隔件。 间隔物的两侧的硅衬底区域具有硅锗图案，其具有突出形状，以具有高于栅极结构的底表面的顶表面; 通过包括围绕所述硅的平坦表面具有角度的花纹，在所述突出部分和所述间隔物之间​​的沟槽部分; 和杂质区域。 沿着硅锗图案和间隔表面的轮廓布置阻挡绝缘膜，同时保持硅锗图案的凹槽与间隔物之间​​的沟槽部分。 绝缘翼图案被安装在隔离绝缘膜的上部分表面上并填充硅锗图案和间隔物之间​​的沟槽部分的形式。