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公开(公告)号：KR1020170037593A
公开(公告)日：2017-04-04
申请号：KR1020170036570
申请日：2017-03-23
Applicant: 삼성전자주식회사
Abstract: 본발명의일 실시예에따른답변추천장치는, 질문에해당하는부모문장에대한데이터와상기질문의답변에해당하는자식문장에대한데이터로이루어진대화쌍데이터를수집하는데이터수집부; 상기수집된대화쌍데이터를전처리하는데이터전처리부; 상기전처리된데이터별로기 설정된축으로구성된좌표계상의특정지점에위치시키는벡터화부; 상기위치된특정지점에관한정보를이용하여클러스터링수행하고기 설정된병합방법에따라서하나의클러스터링내에포함된유사한문장들을병합하는클러스터링부; 상기병합이후에상기클러스터링내에포함된문장별로수신된메시지에대한답변으로적합한정도를점수화하는랭킹부; 상기점수가기 설정된점수보다높은문장이나상기점수가높은순서로기 설정된개수의문장을기 설정된그룹핑기준에따라서그룹핑하는그룹핑부; 및상기그룹핑결과, 동일한그룹에속한문장들은추천답변으로연속적으로제공하지않고서로다른그룹에속한문장들을순차적으로제공하는추천답변제공부를포함할수 있다.
Abstract translation: 根据本发明示例性实施例的答案推荐装置包括：数据收集单元，用于收集包括关于对应于问题的父母句子的数据的对话对数据和与对应于问题的答案的子句子的数据; 数据预处理单元，用于预处理收集的会话对数据; 矢量化单元，用于将预处理数据定位在由预定轴配置的坐标系上的特定点处; 聚类单元，用于使用关于特定位置的信息执行聚类，并根据预定合并方法合并包括在一个聚类中的类似句子; 排序单元，用于针对在合并之后针对聚类中包括的每个句子接收到的消息作出对适当程度的评分; 分组单元，用于根据预定分组标准将具有高于预定分数的分数的句子或具有高分数的预定数量的句子分组; 以及推荐回复提供单元，用于顺序地提供属于不同组的句子，而不连续提供属于作为分组结果的相同组的句子。
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公开(公告)号：KR1020060011432A
公开(公告)日：2006-02-03
申请号：KR1020040060277
申请日：2004-07-30
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76808 , H01L21/76802 , H01L21/76831 , H01L21/76844 , H01L21/76846 , H01L21/76862
Abstract: 반도체 소자의 금속 배선 형성 방법이 제공된다. 반도체 소자의 금속 배선 형성 방법은, 먼저, 도전성 패턴이 매립되어 있는 기판상에 식각 저지막 및 절연막을 순차적으로 형성한다. 다음, 앞서의 결과물을 패터닝하여 식각 저지막이 노출되도록 개구부를 형성한다. 이어, 기판상에 단차를 따라 제1 확산 방지막을 형성한다. 다음, 스퍼터링 방식의 식각을 통하여 개구부 하부의 제1 확산 방지막과 식각 저지막을 제거한다. 이어, 도전성 패턴과 전기적으로 연결되는 도전 물질을 개구부에 매몰시킨다.
스퍼터링, 아르곤 입자, 다마신, 비아홀-
公开(公告)号：KR1020040014710A
公开(公告)日：2004-02-18
申请号：KR1020020047341
申请日：2002-08-10
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a via of a semiconductor device is provided to connect a top copper line to a bottom copper line by forming an oxide layer on a bottom of a via hole, removing selectively the oxide layer, and forming discontinuously a barrier metal layer. CONSTITUTION: A via hole is formed by etching an insulating layer formed on a metal pattern(105) to expose partially the metal pattern(105). The metal pattern exposed by the via hole is oxidized. A lower part of the via hole is enlarged by etching an oxidized part of the metal pattern. The metal pattern is partially exposed by forming a barrier metal layer(160) on a bottom of the via hole corresponding to each size of a side and an entrance of the via hole. The via hole is buried by a metal material.
Abstract translation: 目的：提供一种用于形成半导体器件的通孔的方法，通过在通孔的底部形成氧化层，将顶部铜线连接到底部铜线，选择性地去除氧化物层，并且不连续地形成阻挡金属 层。 构成：通过蚀刻形成在金属图案（105）上的绝缘层以使部分地暴露金属图案（105）而形成通孔。 由通孔露出的金属图案被氧化。 通过蚀刻金属图案的氧化部分来扩大通孔的下部。 通过在通孔的底部形成阻挡金属层（160）来部分地暴露金属图案，该阻挡金属层对应于通孔的侧面和入口的每个尺寸。 通孔被金属材料掩埋。
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公开(公告)号：KR100408743B1
公开(公告)日：2003-12-11
申请号：KR1020010058748
申请日：2001-09-21
Applicant: 삼성전자주식회사
CPC classification number: B82Y20/00 , H01L27/105 , H01L27/1052 , H01L27/10873 , Y10S438/962
Abstract: In a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode including the quantum dot, a first layer including a first material is deposited on the substrate. The first material has first atoms that are superbundant and bound with the weak bonding energy in the first layer. A second layer is deposited on the first layer. The second layer comprises a second material including second atoms that are capable of migrating into the first atoms. The first atoms are migrated into the second layer and the second atoms are migrated into the first layer, so that the second atoms are arranged in the first layer. Each of the second atoms in the first layer is formed into a quantum dot. An electrode layer is formed on the first layer after partially etching the second layer, and then a gate electrode is formed by patterning the electrode layer. Accordingly, The quantum dot can be formed in the semiconductor device in such a manner that a size and a distribution of the quantum dot is easily controlled.
Abstract translation: 在形成具有纳米尺寸的量子点的方法和形成包括量子点的栅电极的方法中，包括第一材料的第一层被沉积在衬底上。 第一种材料具有第一种原子，它们是超级丰富的，并且在第一层中具有弱结合能。 第二层沉积在第一层上。 第二层包括第二材料，第二材料包括能够迁移到第一原子中的第二原子。 第一个原子迁移到第二个层中，第二个原子迁移到第一个层中，以便第二个原子排列在第一个层中。 第一层中的每个第二原子形成量子点。 在部分蚀刻第二层之后，在第一层上形成电极层，然后通过构图电极层形成栅电极。 因此，量子点可以以容易控制量子点的尺寸和分布的方式形成在半导体器件中。
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公开(公告)号：KR1020030025617A
公开(公告)日：2003-03-29
申请号：KR1020010058748
申请日：2001-09-21
Applicant: 삼성전자주식회사
CPC classification number: B82Y20/00 , H01L27/105 , H01L27/1052 , H01L27/10873 , Y10S438/962
Abstract: PURPOSE: A method for forming quantum dots and a method for forming a gate electrode by using the same are provided to form uniformly the quantum dots having a nano size by utilizing material migration. CONSTITUTION: An SiON layer(22) is formed on a substrate(20) by using PECVD(Plasma Enhanced Chemical vapor Deposition) method. The PECVD process is performed by using NH3 gas of 150sccm, N2O gas of 50sccm, and SiH4 gas of 200sccm. Plasma is formed by applying electric power of 100 watt. An Al layer as a conductive layer is formed on the SiON layer(22). The Al layer is formed by a sputtering process using an Al material as a target. A plurality of quantum dots(26) are formed on the SiON layer(22) by performing a thermal process. The SiON layer(22) having the quantum dots(26) is formed on the substrate(20) by etching the Al layer.
Abstract translation: 目的：提供一种用于形成量子点的方法和通过使用该方法形成栅电极的方法，以通过利用材料迁移来均匀地形成具有纳米尺寸的量子点。 构成：通过使用PECVD（等离子增强化学气相沉积）方法在衬底（20）上形成SiON层（22）。 通过使用150sccm的NH 3气体，50sccm的N 2 O气体和200sccm的SiH 4气体进行PECVD处理。 等离子体通过施加100瓦的电力而形成。 在SiON层（22）上形成作为导电层的Al层。 Al层通过使用Al材料作为靶的溅射法形成。 通过进行热处理，在SiON层（22）上形成多个量子点（26）。 通过蚀刻Al层，在基板（20）上形成具有量子点（26）的SiON层（22）。
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Patent Agency Ranking
公开(公告)号：KR1019980026081A
公开(公告)日：1998-07-15
申请号：KR1019960044406
申请日：1996-10-07
Applicant: 삼성전자주식회사
IPC: H01L21/285
Abstract: 스퍼터링 장비가 개시되어 있다. 이 장비는 밀폐된 챔버와, 상기 챔버 내의 바닥에 설치된 지지대와, 상기 지지대의 상부에 설치되어 웨이퍼의 온도를 조절하는 히터블록과, 상기 히터블록에 의해 열전달이 되도록 히터블록 상에 접촉되고 웨이퍼가 놓여지는 척과, 상기 밀폐된 챔버 내의 압력을 조절하기 위하여 상기 챔버의 한 쪽 측벽 외부에 설치된 진공 밸브를 구비하는 스퍼터링 장비에 있어서, 상기 척의 가장자리 전체에 걸쳐서 그 위에 소정의 높이를 갖도록 설치된 패스 쓰루 쉴드를 구비하는 것을 특징으로 한다. 이에 따라, 챔버 내에 형성된 플라즈마 및 타게트로부터 튀어나오는 원자들이 척의 아래로 침투하는 현상을 억제시킬 수 있으므로 척 아래에 설치된 히터블록 표면에 물질막이 형성되는 것을 방지할 수 있다. 따라서, 장비의 세정작업시 히터블록까지 고려해야 하는 문제점을 해결할 수 있으므로 장비의 가동효율을 개선시킬 수 있다.
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公开(公告)号：KR101852905B1
公开(公告)日：2018-06-20
申请号：KR1020170176348
申请日：2017-12-20
Applicant: 삼성전자주식회사
Abstract: 본발명에의하면, 사용자장치에제공되는메시지에서하나이상의키워드가결정되는단계및 결정된키워드에기초하여하나이상의앱(application)을포함하는앱 리스트를표시하는단계를포함하는앱 리스트제공방법을제공할수 있다.
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公开(公告)号：KR1020080051352A
公开(公告)日：2008-06-11
申请号：KR1020060122253
申请日：2006-12-05
Applicant: 삼성전자주식회사
Inventor： 손정훈
IPC: H01L21/28
CPC classification number: H01L21/28518 , H01L21/76814 , H01L21/76826 , H01L21/76877
Abstract: A semiconductor device and a method for manufacturing the same are provided to prevent an upper region of a metal silicide layer from being a resistor of high resistance by preparing silicon on an attacked silicide region. A metal silicide layer is formed on a substrate(100). An interlayer dielectric layer(120) covering the metal silicide layer is formed. The interlayer dielectric layer is patterned to form a contact hole(125). The contact hole exposes at least part of an upper surface of the metal silicide layer. A silicon element is complemented on the metal silicide layer exposed by the contact hole. The metal silicide layer is divided into a first silicide region(110a') and a second silicide layer(110b) by forming the contact hole. The first silicide layer occupies an upper region including an upper surface exposed by the contact hole. The second silicide region occupies the remaining region except for the first silicide region.
Abstract translation: 提供半导体器件及其制造方法，以通过在受侵蚀的硅化物区域上制备硅来防止金属硅化物层的上部区域成为高电阻的电阻器。 在基板（100）上形成金属硅化物层。 形成覆盖金属硅化物层的层间绝缘层（120）。 图案化层间电介质层以形成接触孔（125）。 接触孔露出金属硅化物层的上表面的至少一部分。 在由接触孔暴露的金属硅化物层上补充硅元素。 金属硅化物层通过形成接触孔而被分成第一硅化物区域（110a）和第二硅化物层（110b）。 第一硅化物层占据包括由接触孔暴露的上表面的上部区域。 第二硅化物区域占据除了第一硅化物区域之外的剩余区域。
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公开(公告)号：KR100455366B1
公开(公告)日：2005-01-17
申请号：KR1019970020980
申请日：1997-05-27
Applicant: 삼성전자주식회사
IPC: H01L21/302
Abstract: PURPOSE: A method for removing residue in fabricating a semiconductor device is provided to improve coating of a titanium/titanium nitride layer formed before tungsten is deposited and bury tungsten without generating a void by avoiding outgassing caused by titanium remnants. CONSTITUTION: The first structure in which a silicon layer and a silicidation preventing layer(46) are stacked is formed in one region of a semiconductor substrate(40). The second structure in which only a silicon layer is stacked is formed in the other region of the semiconductor substrate. After titanium is deposited on the first and second structures, a heat treatment for silicidation is performed. The remaining titanium on the first structure is sputter-etched.
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公开(公告)号：KR1020040108032A
公开(公告)日：2004-12-23
申请号：KR1020030038770
申请日：2003-06-16
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A semiconductor device with a contact structure and a forming method thereof are provided to protect a lower conductive pattern from damage under a damascene pattern forming process by using a capping layer. CONSTITUTION: A lower conductive pattern(110) is formed on a semiconductor substrate(101). A capping layer(115) is formed on the lower conductive pattern. A mold layer(122) is formed thereon. A damascene pattern for exposing a predetermined portion of the lower conductive pattern to the outside is formed through the mold layer and the capping layer. An upper conductive pattern(133a) is filled in the damascene pattern. The capping layer is an oxide layer, wherein the oxide layer is formed by performing a low temperature oxidation on the lower conductive pattern.
Abstract translation: 目的：提供一种具有接触结构及其形成方法的半导体器件，以通过使用覆盖层来保护下部导电图案免受在镶嵌图案形成工艺下的损坏。 构成：在半导体衬底（101）上形成下导电图案（110）。 在下导电图案上形成封盖层（115）。 在其上形成模具层（122）。 通过模层和覆盖层形成用于将下导电图案的预定部分暴露于外部的镶嵌图案。 上部导电图案（133a）填充在镶嵌图案中。 覆盖层是氧化物层，其中通过在下导电图案上进行低温氧化而形成氧化物层。
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