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公开(公告)号：KR1020160017580A
公开(公告)日：2016-02-16
申请号：KR1020140126730
申请日：2014-09-23
Applicant: 삼성전자주식회사
Abstract: 본발명의스토리지장치는읽기, 쓰기, 및소거를수행하는불휘발성메모리및 메모리컨트롤러를포함한다. 상기메모리컨트롤러는허용범위내의기준전압레벨로설정된전압신호를상기불휘발성메모리와교환하거나외부로부터수신하는동작모드로동작할수 있다. 상기메모리컨트롤러가동작모드로동작시, 메모리컨트롤러는상기전압신호의전압레벨및 온도에따라상기불휘발성메모리의동작주파수를최적화할수 있다.
Abstract translation: 根据本发明，存储装置包括非易失性存储器和存储器控制器，其中非易失性存储器执行读，写和擦除操作。 存储器控制器在操作模式下操作，其中存储器控制器将设置为可允许范围内的参考电压电平的电压信号与非易失性存储器交换或从外部设备接收电压信号。 当存储器控制器在操作模式下操作时，存储器控制器根据电压信号的电压电平和温度优化非易失性存储器的工作频率。
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Patent Agency Ranking
公开(公告)号：KR1020090131954A
公开(公告)日：2009-12-30
申请号：KR1020080057973
申请日：2008-06-19
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C7/16 , G11C11/5628
Abstract: PURPOSE: A memory card using multilevel signaling and a memory system including the memory card are provided to improve a data transfer rate between a memory controller and a flash memory. CONSTITUTION: A memory interface(122) outputs a write data signal to be written in a flash memory(130). A multilevel converter(124) converts the write data signal into a write voltage signal. The multilevel converter offers the converted write voltage signal to the flash memory. The write voltage signal has different voltage levels according to values of plural bits of the write data signal. The multilevel converter restores a read voltage signal read from the flash memory into a read data signal consisting of plural bits.
Abstract translation: 目的：提供使用多级信令的存储卡和包括存储卡的存储器系统，以提高存储器控制器和闪速存储器之间的数据传输速率。 构成：存储器接口（122）输出要写入闪速存储器（130）的写入数据信号。 多电平转换器（124）将写入数据信号转换成写入电压信号。 多电平转换器将转换的写入电压信号提供给闪存。 写入电压信号根据写入数据信号的多个位的值而具有不同的电压电平。 多电平转换器将从闪存读取的读取电压信号恢复为由多个位组成的读取数据信号。
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公开(公告)号：KR1020130114303A
公开(公告)日：2013-10-17
申请号：KR1020120036515
申请日：2012-04-09
Applicant: 삼성전자주식회사
CPC classification number: G06F11/10 , G06F11/1052
Abstract: PURPOSE: A method of operating a memory controller and devices including the memory controller improve the performance of a read operation by controlling the output timing of an error corrected first chunk. CONSTITUTION: Error correction is performed from first to (N-1)^th chunks among object data including N (N is integer) chunks (S10). It is determined that coefficients of an order term equal to or greater than a reference order term of an error location polynomial expression are all 0 for the N^th chunk among the N chunks (S40). The output timing of the error corrected first chunk is controlled based on the determined result. [Reference numerals] (AA) Start a read action; (BB) End the read action; (S10) Correct errors from a first chunk to a (N-1)^th chunk in a chunk-by-chunk manner; (S20) Store a N^th chunk in a memory device; (S30) Calculate syndrom values for the N^th chunk; (S40) Are the coefficients of the N^th chunk equal to or larger than a reference order term of an error location polynomial expression all 0 ?; (S51) Output the chunks in which errors are corrected in order with the first chunk being the start, while the N^th chunk is corrected; (S52) Calculate the values of the error location polynomial expression; (S53) Output the N^th chunk with its errors corrected; (S54) Correct the N^th chunk's errors; (S56) Output the chunks in which errors are corrected in order with the first chunk being the start and the N^th chunk being the ending point
Abstract translation: 目的：操作存储器控制器的方法和包括存储器控制器的设备通过控制纠错第一块的输出定时来提高读取操作的性能。 构成：在包括N（N是整数）块的对象数据中，从第一到第（N-1）^个块执行纠错（S10）。 确定等于或大于错误位置多项式表达式的参考顺序项的顺序项的系数对于N个块中的第N个块都是0（S40）。 基于确定的结果来控制纠错的第一块的输出定时。 （附图标记）（AA）开始读取动作; （BB）结束阅读动作; （S10）以逐块方式从第一块到第（N-1）块块纠正错误; （S20）将N ^块存储在存储装置中; （S30）计算第N个块的综合征值; （S40）第N个块的系数是否等于或大于错误位置多项式表达式的参考顺序项全部为0？ （S51）以第一个块为开始的顺序输出校正错误的块，而第N个块被校正; （S52）计算误差位置多项式的值; （S53）输出错误修正的第N个块; （S54）纠正第N个块的错误; （S56）以第一个块为开始的顺序输出修正错误的块，第N个块为终点
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公开(公告)号：KR1020140041207A
公开(公告)日：2014-04-04
申请号：KR1020120108271
申请日：2012-09-27
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1078 , G11C5/063 , G11C7/22 , G11C2207/2272
Abstract: A method for compensating data skew in a memory device and a memory controller adopting the same are disclosed. The method for compensating data skew comprises the steps of measuring at least one factor value affecting the data skew of a memory system; and adjusting a delay amount of a data strobe signal based on the measured factor value, wherein the factor value includes at least one of a level value and a temperature value of an internal voltage used by the memory system. [Reference numerals] (AA) Start; (BB) End; (S110) Measuring at least one factor value affecting the data skew; (S120) Adjusting a delay amount of a data strobe signal based on the measured factor value
Abstract translation: 公开了一种用于补偿存储器件中的数据偏移的方法和采用该偏移的存储器控制器。 用于补偿数据偏移的方法包括测量影响存储器系统的数据偏移的至少一个因子值的步骤; 以及基于测量的因子值来调整数据选通信号的延迟量，其中所述因子值包括存储器系统使用的内部电压的电平值和温度值中的至少一个。 （附图标记）（AA）开始; （BB）结束; （S110）测量影响数据偏移的至少一个因子值; （S120）基于测量的因子值调整数据选通信号的延迟量
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公开(公告)号：KR101521997B1
公开(公告)日：2015-05-22
申请号：KR1020080057973
申请日：2008-06-19
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C7/16 , G11C11/5628
Abstract: 본발명의메모리카드는, 플래시메모리와, 상기플래시메모리에기입될기입데이터신호를출력하는메모리인터페이스, 그리고상기기입데이터신호를기입전압신호로변환해서상기플래시메모리로제공하는멀티레벨변환기를포함하며, 상기기입전압신호는상기기입데이터신호의복수의비트들의값에따라서서로다른전압레벨을갖는다. 메모리컨트롤러와플래시메모리간의멀티레벨시그널링에의해서데이터전송속도가향상된다.
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