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1.发明公开
公开(公告)号：KR1020140088421A
公开(公告)日：2014-07-10
申请号：KR1020130000280
申请日：2013-01-02
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F2212/7207
Abstract: The present invention relates to a programming method of a nonvolatile memory. The programming method of the present invention comprises the steps of: generating first to m^th meta data based on first to m^th data; generating rearranged first to m^th meta data by rearranging the first to m^th meta data; and programming the rearranged first to m^th meta data and the first to m^th data in first to m^th pages, respectively.
Abstract translation: 非易失性存储器的编程方法技术领域本发明涉及非易失性存储器的编程方法。 本发明的编程方法包括以下步骤：基于第一到第m个数据产生第一到第m个元数据; 通过重新排列第一到第m个元数据来产生重新排列的第一到第m个元数据; 并分别对第一至第m个第一个元数据和第一至第m个数据进行编程。
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公开(公告)号：KR1020120125890A
公开(公告)日：2012-11-19
申请号：KR1020110043619
申请日：2011-05-09
Applicant: 삼성전자주식회사
CPC classification number: H03M13/1545 , G06F1/3225 , G06F1/3275 , G06F11/1048 , H03M13/09 , H03M13/152 , H03M13/3715 , Y02D10/13 , Y02D10/14
Abstract: PURPOSE: A memory controller and a method for operating the same are provided to reduce the power consumption of an error correction decoder according to the number of measured errors after the number of the errors of a read vector is measured. CONSTITUTION: An error correction encoder encodes a write data vector to a code vector(S110). The code vector is written in the memory device(S120). A read vector is read from the memory device(S130). An error correction decoder corrects the errors of the read vector by controlling power consumption per cycle according to the number of the errors of the read vector(S140).
Abstract translation: 目的：提供一种存储器控制器及其操作方法，以便在测量读取向量的误差数后，根据测量误差的数量来减少纠错解码器的功耗。 构成：纠错编码器将写数据向量编码为码矢量（S110）。 代码矢量写入存储器件（S120）。 从存储器件读取读取矢量（S130）。 纠错解码器通过根据读取向量的错误数量控制每个周期的功耗来校正读取向量的错误（S140）。
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公开(公告)号：KR1020080065116A
公开(公告)日：2008-07-11
申请号：KR1020070002103
申请日：2007-01-08
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628
Abstract: A multi level cell flash memory device and a program method thereof are provided to perform flexible program for various requirements of a system, by performing the program regardless of the sequence of bits of multi bit data. According to a program method of a multi level cell flash memory device, a memory cell selected through plural program procedures is programmed with multi bit data(11,10,01,00). Data to be stored in the selected memory cell in the present program procedure is determined by the data of the selected memory cell and the present program procedure. According to the present program procedure, an address of bits programmed in the present program procedure is detected. The data of the selected memory cell is read. Target data is determined by referring to the detected address and the data of the selected memory cell.
Abstract translation: 提供多级单元闪存器件及其程序方法，通过执行程序来执行用于系统的各种要求的灵活程序，而不管多位数据的位序列如何。 根据多电平单元闪存器件的编程方法，通过多个程序程序选择的存储器单元用多位数据（11,10,01,00）进行编程。 要存储在当前程序过程中的所选存储单元中的数据由所选存储单元的数据和当前的程序程序确定。 根据本程序程序，检测在本程序程序中编程的位地址。 读取所选存储单元的数据。 通过参考检测到的地址和所选存储单元的数据来确定目标数据。
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公开(公告)号：KR101747794B1
公开(公告)日：2017-06-16
申请号：KR1020110028318
申请日：2011-03-29
Applicant: 삼성전자주식회사
CPC classification number: H03M13/6561 , H03M13/1525 , H03M13/1545 , H03M13/37
Abstract: 본발명에따른저장매체로부터의독출데이터를처리하는에러정정디코더는, 복수의채널들각각으로전달되는채널데이터들의신드롬들을계산하는신드롬계산블록, 상기신드롬들을참조하여상기채널데이터들각각에대한에러위치다항식들을구하는에러위치다항식계산블록, 그리고상기에러위치다항식들각각의해를구하는치엔서치블록을포함하되, 상기에러위치다항식계산블록또는상기치엔서치블록은상기복수의채널들각각에독립적으로구동되며, 상기복수의채널들중 임의로선택된어느하나의채널의채널데이터를처리하는적어도하나의계산유닛을포함한다.
Abstract translation: 用于处理所述存储介质robuteoui按照本发明，参照出错计算块读取的数据的纠错解码器中，校正子计算的信道数据的综合征要由误差为每个所述信道数据位置的传输给每个所述多个通道中的 获得错误定位多项式的计算，并包括Chien搜索块中，通过以分别获得的多项式块所述错误位置多项式和误差定位子多项式计算块或Chien搜索块中的每个的多个通道中的每一个独立地驱动， 以及至少一个计算单元，用于处理多个频道中的任何一个频道的频道数据。
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Patent Agency Ranking
公开(公告)号：KR1020120110450A
公开(公告)日：2012-10-10
申请号：KR1020110028318
申请日：2011-03-29
Applicant: 삼성전자주식회사
CPC classification number: H03M13/6561 , H03M13/1525 , H03M13/1545 , H03M13/37 , G06F11/1068
Abstract: PURPOSE: An error correction decoder and an error correcting method thereof are provided to reduce the size of the error correction decoder by decreasing the number of intelligent devices for the error correction decoding of channel data. CONSTITUTION: A syndrome calculation block(410) calculates the syndromes of channel data transmitted to a plurality of channels. An error location polynomial calculation block produces error location polynomials for channel data by referring to the syndromes. A chien search block(430) obtains each solutions of the error location polynomial. The error location polynomial calculation block or chien search block is driven independently of the plurality of the channels and includes a calculation unit which calculates the channel data of the arbitrarily selected channel.
Abstract translation: 目的：提供一种纠错解码器及其纠错方法，通过减少用于频道数据的纠错解码的智能装置的数量来减小纠错解码器的大小。 构成：校正子计算块（410）计算发送到多个信道的信道数据的综合性。 误差位置多项式计算块通过参照校正子产生通道数据的误差位置多项式。 奇维搜索块（430）获得错误位置多项式的每个解。 误差位置多项式计算块或奇数搜索块独立于多个信道被驱动，并且包括计算单元，其计算任意选择的信道的信道数据。
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公开(公告)号：KR1020120029154A
公开(公告)日：2012-03-26
申请号：KR1020100091068
申请日：2010-09-16
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1008 , G06F11/108 , H03M13/1515 , H03M13/152 , H03M13/1545 , H03M13/6502
Abstract: PURPOSE: A decoder, an operating method thereof, and apparatuses having the same are provided to prevent power consumption by controlling a frequency of a clock signal provided to a chien search block according to information about the highest degree term of an error locator polynomial. CONSTITUTION: A frequency control logic(62) determines a frequency of a clock signal for being generated from a clock oscillator. The frequency control logic generates frequency information, in other word, information for the frequency of the clock signal generated from the clock oscillator. An oscillator trimming logic(64) receives the frequency information outputted from the frequency control logic. The oscillator trimming logic generates a control signal for controlling the operation of the clock oscillator according to the frequency information received. A frequency DB(66) stores the information about the number of errors and the information about the frequency of the clock signal in a frequency mapping table.
Abstract translation: 目的：提供一种解码器及其操作方法，以及具有该解码器及其操作方法的装置，以通过根据关于误差定位多项式的最高度项的信息来控制提供给搜索块的时钟信号的频率来防止功耗。 构成：频率控制逻辑（62）确定从时钟振荡器产生的时钟信号的频率。 频率控制逻辑产生频率信息，换句话说，产生从时钟振荡器产生的时钟信号的频率的信息。 振荡器调整逻辑（64）接收从频率控制逻辑输出的频率信息。 振荡器调整逻辑根据所接收的频率信息产生用于控制时钟振荡器的操作的控制信号。 频率DB（66）将关于错误数量的信息和关于时钟信号的频率的信息存储在频率映射表中。
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8.发明授权듀얼-신드롬 생성기를 포함하는 에러 정정 코드 블록, 이의 동작 방법, 및 상기 에러 정정 코드 블록을 포함하는 시스템 有权一种包括双校验值生成器的纠错码块，其操作方法以及包括纠错码块的系统
公开(公告)号：KR101807538B1
公开(公告)日：2017-12-12
申请号：KR1020110104928
申请日：2011-10-14
Applicant: 삼성전자주식회사
IPC: H03M13/05
CPC classification number: H03M13/1515 , G06F11/10 , H03M13/152 , H03M13/1545 , H03M13/159 , H03M13/6561
Abstract: 레이턴시(latency) 없이연속적인다수의코드워드들을처리할수 있는듀얼-신드롬발생기를포함하는에러정정코드블록은상기듀얼-신드롬발생기중에서어느하나를이용하여상기다수의코드워드들중에서해당하는짝수번째코드워드에대한신드롬값들을계산하고상기듀얼-신드롬발생기중에서다른하나를이용하여상기다수의코드워드들중에서해당하는홀수번째코드워드에대한신드롬값들을계산한다.
Abstract translation: 纠错码块是双包括校正子发生器 - 对之间使用多个码字中的任何一个从校正子发生器延迟双和能够处理无（等待时间）的连续的多个码字的偶数码 使用另一个双重校正子发生器来计算多个码字中的奇数编码字的校正子值。
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