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    ＴＳＶ를 포함하는 반도체 소자
    4.
    发明公开
    ＴＳＶ를 포함하는 반도체 소자 无效
    包含TSV（通过硅胶）的半导体器件

    公开(公告)号：KR1020130054005A

    公开(公告)日：2013-05-24

    申请号：KR1020110119772

    申请日：2011-11-16

    Applicant: 삼성전자주식회사

    Inventor： 김석호 ,  최길현 ,  박병률 ,  정현수 ,  신창우 ,  피재현 ,  박연상

    IPC: H01L23/48 ,  H01L23/045 ,  H01L23/055

    CPC classification number: H01L2224/06181 ,  H01L2224/16146 ,  H01L2224/18 ,  H01L2924/00012

    Abstract: PURPOSE: A semiconductor device including a TSV is provided to increase mechanical strength by performing a front etching process. CONSTITUTION: A line layer(130) is formed on the upper surface of a substrate(110). A penetration silicon via passes through the substrate. The via is electrically connected to the line layer. The lower end of the via is protruded from the lower surface of the substrate. The lateral surface of the lower end part is covered with silicon.

    Abstract translation: 目的：提供包括TSV的半导体器件，以通过执行前蚀刻工艺来增加机械强度。 构成：在衬底（110）的上表面上形成线层（130）。 穿透硅通孔穿过基底。 通孔电连接到线路层。 通孔的下端从基板的下表面突出。 下端部的侧面被硅覆盖。

    반도체 장치 및 그 형성방법
    5.
    发明公开
    반도체 장치 및 그 형성방법 失效
    半导体器件及其形成方法

    公开(公告)号：KR1020080063613A

    公开(公告)日：2008-07-07

    申请号：KR1020070000240

    申请日：2007-01-02

    Applicant: 삼성전자주식회사

    Inventor： 최주일 ,  조차제 ,  김석호 ,  신창우 ,  조차제

    IPC: H01L21/60 ,  H01L23/12

    CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05181 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2224/05599

    Abstract: A semiconductor device and a method for fabricating the same are provided to prevent voids or concave portions on a through silicon via by implementing a seed metal film on a lower portion of a hole. A semiconductor device includes a semiconductor substrate(300), a through silicon via(350), an insulation pattern(310), and an alloy conductive pattern(320). The through silicon via penetrating the semiconductor substrate is protruded from a lower surface of the semiconductor substrate. The insulation pattern is formed between the through silicon via and the semiconductor substrate. The alloy conductive pattern is formed between the insulation pattern and the through silicon via. The through silicon via includes a seed metal film at a lower portion thereof.

    Abstract translation: 提供半导体器件及其制造方法，以通过在孔的下部实施种子金属膜来防止通孔硅通孔上的空隙或凹部。 半导体器件包括半导体衬底（300），贯通硅通孔（350），绝缘图案（310）和合金导电图案（320）。 穿过半导体衬底的贯通硅从半导体衬底的下表面突出。 绝缘图案形成在贯通硅通孔和半导体基板之间。 在绝缘图案和通过硅通孔之间形成合金导电图案。 贯通硅通孔在其下部包括种子金属膜。

    반도체 스택 패키지 및 그의 제조 방법
    6.
    发明授权
    반도체 스택 패키지 및 그의 제조 방법 失效
    堆叠式半导体封装及其制造方法

    公开(公告)号：KR100829614B1

    公开(公告)日：2008-05-14

    申请号：KR1020060137912

    申请日：2006-12-29

    Applicant: 삼성전자주식회사

    Inventor： 조차제 ,  김석호 ,  최주일 ,  신창우

    IPC: H01L23/28

    CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/48463 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19107

    Abstract: A semiconductor stack package and a manufacturing method thereof are provided to simplify a manufacturing process of the stack package by simply forming an interconnection layer using an electroless plating process and an electrolyte plating process. A semiconductor stack package includes a substrate(170), plural semiconductor packages(110,120,130), an interconnection layer(150), and a conductive reinforcement layer(160). The semiconductor packages are laminated on the substrate and include conductive lines, which are exposed from edge portions thereof. The interconnection layer is formed on the edge portion of the semiconductor package and electrically couples the conductive lines with each other. The conductive reinforcement layer is formed on the interconnection layer and reinforces an electrical coupling property between the conductive lines and the interconnection layer.

    Abstract translation: 提供一种半导体堆叠封装及其制造方法，通过简单地使用化学镀处理和电解电镀工艺形成互连层来简化堆叠封装的制造工艺。 半导体堆叠封装包括衬底（170），多个半导体封装（110,120,130），互连层（150）和导电加强层（160）。 半导体封装层叠在基板上，并且包括从其边缘部分露出的导电线。 互连层形成在半导体封装的边缘部分上并将导线彼此电耦合。 导电加强层形成在互连层上，并加强导电线和互连层之间的电耦合性能。

    뉴로모픽 칩에서 스파이크 이벤트를 송수신하는 송수신 장치 및 방법
    8.
    发明授权
    뉴로모픽 칩에서 스파이크 이벤트를 송수신하는 송수신 장치 및 방법 有权
    收发器和方法发送和接收尖峰事件在一个新的Lomographic芯片

    公开(公告)号：KR101838560B1

    公开(公告)日：2018-03-15

    申请号：KR1020110074388

    申请日：2011-07-27

    Applicant: 삼성전자주식회사 ,  포항공과대학교 산학협력단

    Inventor： 심재윤 ,  이준행 ,  류현석 ,  박근주 ,  신창우

    IPC: G06N3/063

    CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/0635

    Abstract: 뉴로모픽칩에서스파이크이벤트를송수신하는송수신장치및 방법이제공된다. 일측면에따른뉴로모픽칩의송신장치는어드레스들을순차적으로반복해서어드레스버스에출력하고, 스파이크가수신되면, 순차적으로반복해서출력되는어드레스가스파이크를출력한뉴런의어드레스와동일하게되는가장빠른시점에서스트로브(strobe)를출력한다. 그리고, 뉴로모픽칩의수신장치는스트로브가수신되면, 스트로브가감지된시점에어드레스버스를통해수신되는어드레스를입력어드레스로확인한다.

    Abstract translation: 提供了用于在神经模块芯片中发送和接收尖峰事件的发送和接收设备和方法。 根据一个方面，新提供了pikchip的发射机是在时间上最早的点时反复的地址依次输出到地址总线，和尖峰已被接收，即是反复顺序的地址将其输出为输出尖峰神经元的地址 并输出一个选通信号。 当接收到选通脉冲时，神经模块芯片的接收装置确认在检测到选通脉冲作为输入地址时通过地址总线接收的地址。

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