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公开(公告)号：KR1020000042243A
公开(公告)日：2000-07-15
申请号：KR1019980058368
申请日：1998-12-24
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A contact forming method of a semiconductor device is to prevent a recess and a crack of a tungsten layer from generating. CONSTITUTION: A method for manufacturing a semiconductor device comprises the steps of: depositing an insulating layer(102) on an upper portion of a semiconductor substrate; etching the insulating layer and forming a contact hole(103); forming a first barrier layer(104) on an upper portion of resultant material with the contact hole formed therein; depositing a first tungsten layer(106) on the upper portion of the first barrier layer; forming a second barrier metal layer(108) on the upper portion of the first tungsten layer; depositing a second tungsten layer(110) on the upper portion of the second barrier metal layer and etching back the second tungsten layer; etching back the exposed second barrier metal layer; etching back the exposed first tungsten layer; and forming a tungsten plug including the second barrier metal layer within the contact hole by etching back the exposed first barrier metal layer.
Abstract translation: 目的：半导体器件的接触形成方法是防止发生钨层的凹陷和裂纹。 构成：制造半导体器件的方法包括以下步骤：在半导体衬底的上部沉积绝缘层（102）; 蚀刻绝缘层并形成接触孔（103）; 在其中形成有接触孔的所得材料的上部上形成第一阻挡层（104）; 在第一阻挡层的上部上沉积第一钨层（106）; 在所述第一钨层的上部形成第二阻挡金属层（108）; 在所述第二阻挡金属层的上部上沉积第二钨层（110）并蚀刻所述第二钨层; 蚀刻暴露的第二阻挡金属层; 蚀刻暴露的第一钨层; 以及通过蚀刻暴露的第一阻挡金属层，在接触孔内形成包括第二阻挡金属层的钨塞。
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公开(公告)号：KR1020000033434A
公开(公告)日：2000-06-15
申请号：KR1019980050284
申请日：1998-11-23
Applicant: 삼성전자주식회사
IPC: H01L21/02
Abstract: PURPOSE: A fabrication method of a flash memory device is provided to reduce a space CD(critical dimension) between floating gates by using simplified processing. CONSTITUTION: After defining an active region in a semiconductor substrate(100) by forming a field oxide(102) on the semiconductor substrate, a tunnel oxide(104) is formed on the active region. After forming a floating gate(106) on the resultant structure, a photoresist pattern(108) is formed on the floating gate(106). A substance layer(110) is deposited on the resultant structure and etching the substance layer(110), thereby forming spacers(110a) at both side walls of the photoresist pattern(108). The floating gate(106) is etched by using the spacers(110a) as a mask. Then, the photoresist pattern(108) and the spacers(110a) are removed.
Abstract translation: 目的：提供一种闪速存储器件的制造方法，以通过使用简化的处理来减少浮动栅极之间的空间CD（临界尺寸）。 构成：在半导体衬底（100）中通过在半导体衬底上形成场氧化物（102）来限定有源区域之后，在有源区上形成隧道氧化物（104）。 在所得结构上形成浮栅（106）之后，在浮动栅（106）上形成光刻胶图案（108）。 物质层（110）沉积在所得结构上并蚀刻物质层（110），从而在光致抗蚀剂图案（108）的两个侧壁处形成间隔物（110a）。 通过使用间隔物（110a）作为掩模来蚀刻浮置栅极（106）。 然后，去除光致抗蚀剂图案（108）和间隔物（110a）。
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公开(公告)号：KR1020000018303A
公开(公告)日：2000-04-06
申请号：KR1019980035833
申请日：1998-09-01
Applicant: 삼성전자주식회사
IPC: H01L21/24
Abstract: PURPOSE: A contact hole formation method is provided to simultaneously form a self-align contact and a butting contact without stopping and residues by using improved etchants. CONSTITUTION: An etch stopping layer(20) and an interlayer insulator(22) are sequentially deposited on a semiconductor substrate(10) having a transistor. Then, two-step etching processes are performed to form a contact hole. The two-step etching comprises firstly etching the interlayer insulator(22) and the etch stopping layer(20) using an etchant contained C2F6, CH3F, and O2, thereby preventing a stopping phenomenon and a residue generation due to O2, and secondly etching using C4F6, CH3F, CO and Ar as an etchant, thereby simultaneously forming the contact hole for butting contact and self-align contact.
Abstract translation: 目的：提供接触孔形成方法，以通过使用改进的蚀刻剂同时形成自对准接触和对接接触而不停止和残留。 构成：在具有晶体管的半导体衬底（10）上顺序地沉积蚀刻停止层（20）和层间绝缘体（22）。 然后，进行两步蚀刻处理以形成接触孔。 两步蚀刻包括首先使用含有C 2 F 6，CH 3 F和O 2的蚀刻剂蚀刻层间绝缘体（22）和蚀刻停止层（20），从而防止由于O 2引起的停止现象和残留物产生，并且其次使用 C4F6，CH3F，CO和Ar作为蚀刻剂，从而同时形成用于对接和自对准接触的接触孔。
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Patent Agency Ranking
公开(公告)号：KR1020000042812A
公开(公告)日：2000-07-15
申请号：KR1019980059094
申请日：1998-12-26
Applicant: 삼성전자주식회사
IPC: H01L21/31
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to manufacture a semiconductor by using a Dual Damascene technique. CONSTITUTION: A method for manufacturing a semiconductor device comprises the following steps. A first insulating layer(102) and an etch barrier are formed on an upper portion of a lower conductive layer(100). A thin hole is formed by etching the etch barrier and the first insulating layer. A side wall insulating layer is formed at an inner portion of the thin hole in order to minimize or reduce a critical dimension of a via-hole. A second insulating layer(114) is formed on the etch barrier including the side wall insulating layer. A trench and the via-hole are formed on the second and the first insulating layers by etching the second insulating layer. A wiring(121) and a via-contact(123) are formed simultaneously by filling the trench and the via-hole with a conductive material.
Abstract translation: 目的：提供一种制造半导体器件的方法，通过使用双镶嵌技术制造半导体。 构成：制造半导体器件的方法包括以下步骤。 在下导电层（100）的上部形成有第一绝缘层（102）和蚀刻阻挡层。 通过蚀刻蚀刻阻挡层和第一绝缘层形成细孔。 侧壁绝缘层形成在薄孔的内部，以便最小化或减小通孔的临界尺寸。 在包括侧壁绝缘层的蚀刻阻挡层上形成第二绝缘层（114）。 通过蚀刻第二绝缘层，在第二绝缘层和第一绝缘层上形成沟槽和通孔。 通过用导电材料填充沟槽和通孔来同时形成布线（121）和通孔接触（123）。
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公开(公告)号：KR1020000009277A
公开(公告)日：2000-02-15
申请号：KR1019980029554
申请日：1998-07-22
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a contact hole in a semiconductor memory device is provided to reduce a maximum size of the contact hole, so that a short between the embedded contact and a neighbor conductive film is prevented. CONSTITUTION: According to the forming method, an etching process is performed to an insulation film(104) where a conductive film is formed by a mask of photoresist film pattern(112), so that a hole(114) whose depth is deeper than a width of the conductive film is formed. Next, A side-wall insulation film(116) is formed in the formed hole(114). Last, the hole(114) where the side-wall insulation film(116) is formed is etched deeply with a maximum depth, so that a contact hole(118) is formed. Thereby, the maximum size of the contact hole(118) can be reduced by the side-wall insulation film(116).
Abstract translation: 目的：提供一种在半导体存储器件中形成接触孔的方法，以减小接触孔的最大尺寸，从而防止嵌入触点和相邻导电膜之间的短路。 构成：根据该形成方法，对通过光致抗蚀剂膜图案（112）的掩模形成导电膜的绝缘膜（104）进行蚀刻处理，使得深度比深度深的孔（114） 形成导电膜的宽度。 接下来，在成形孔（114）中形成侧壁绝缘膜（116）。 最后，形成侧壁绝缘膜（116）的孔（114）以最大深度深度地蚀刻，从而形成接触孔（118）。 由此，可以通过侧壁绝缘膜（116）来减小接触孔（118）的最大尺寸。
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公开(公告)号：KR1020000067132A
公开(公告)日：2000-11-15
申请号：KR1019990014667
申请日：1999-04-23
Applicant: 삼성전자주식회사
IPC: H01L21/82
Abstract: PURPOSE: A method for manufacturing a contact of a semiconductor device is provided to form a finer cell pad contact, by forming a groove having a spacer in a desired region for the cell pad contact, by forming an opening for the cell pad contact through the groove, and by filling the opening with a conductive material. CONSTITUTION: An interlayer dielectric(112) is formed on a semiconductor substrate(100) having an access transistor. The interlayer dielectric is etched by a predetermined thickness to form a groove of a predetermined depth in a desired position for a contact. After a sidewall insulating layer(120) is formed inside the groove, the interlayer dielectric is completely etched along a pattern of the groove having the sidewall insulating layer to form a contact hole covering a predetermined region of the semiconductor substrate. A fine contact is completed by filling up the contact hole with a conductive layer.
Abstract translation: 目的：提供一种用于制造半导体器件的接触的方法，以通过在电池垫接触的所需区域中形成具有间隔物的凹槽来形成更细的电池焊盘接触，通过形成用于电池焊盘接触的开口 槽，并且通过用导电材料填充开口。 构成：在具有存取晶体管的半导体衬底（100）上形成层间电介质（112）。 将层间电介质蚀刻预定厚度，以形成用于接触的所需位置的预定深度的凹槽。 在沟槽内形成侧壁绝缘层（120）之后，沿着具有侧壁绝缘层的凹槽的图案完全蚀刻层间电介质，以形成覆盖半导体衬底的预定区域的接触孔。 通过用导电层填充接触孔来完成精细的接触。
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公开(公告)号：KR1020000040317A
公开(公告)日：2000-07-05
申请号：KR1019980055905
申请日：1998-12-17
Applicant: 삼성전자주식회사
IPC: H01L21/306
Abstract: PURPOSE: A method of manufacturing a semiconductor device is to allow HSQ(Hydrogensilsesquioxane) or FOx(Flowable Oxide) to be etched with high selectivity, without decreasing an etching rate. CONSTITUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a first insulating film(102) on a lower conductive film(100); forming a stopper film(104) on a prescribed area of the first insulating film to protect the first insulting film from the subsequent etching process; forming a second insulating film(106) on the first insulating film on which the stopper film has been formed; and etching the second insulating film and the first insulating film using an etchant having excellent etching selection ratio against the lower conductive film and the stopper film, to make a trench(112) for a wiring and a via hole(114) for a via contact.
Abstract translation: 目的：制造半导体器件的方法是允许在不降低蚀刻速率的情况下以高选择性蚀刻HSQ（Hydrogensilsesquioxane）或FOx（可流动氧化物）。 构成：制造半导体器件的方法包括以下步骤：在下导电膜（100）上形成第一绝缘膜（102）; 在所述第一绝缘膜的规定区域上形成阻挡膜（104），以保护所述第一绝缘膜不受后续蚀刻工艺的影响; 在其上形成有阻挡膜的第一绝缘膜上形成第二绝缘膜（106）; 以及使用相对于下导电膜和阻挡膜具有优良蚀刻选择率的蚀刻剂来蚀刻第二绝缘膜和第一绝缘膜，以形成用于布线的沟槽（112）和用于通孔接触的通孔（114） 。
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公开(公告)号：KR1020000033432A
公开(公告)日：2000-06-15
申请号：KR1019980050282
申请日：1998-11-23
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a boardless contact is provided to prevent degradation of operation speed due to an aerial capacitance. CONSTITUTION: A low dielectricity layer is formed on a lower insulation layer of a semiconductor substrate. Next, area at which a line/space pattern is formed on the low dielectricity layer is etched away. Next, a metal layer is formed on the result area. Next, the metal layer is etched until surface of the low dielectricity layer is exposed, so that the line/space pattern is formed. Next, an upper insulation layer is formed on the result area. Next, the upper insulation layer is etched so that the line/space pattern is exposed.
Abstract translation: 目的：提供一种形成无板接触的方法，以防止由于空中电容引起的操作速度的降低。 构成：在半导体衬底的下绝缘层上形成低介电层。 接下来，蚀刻掉在低介电层上形成线/空间图案的区域。 接下来，在结果区域上形成金属层。 接下来，蚀刻金属层，直到露出低介电层的表面，从而形成线/空间图案。 接下来，在结果区域上形成上绝缘层。 接下来，蚀刻上绝缘层，使得线/空间图案暴露。
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