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公开(公告)号：KR100389929B1
公开(公告)日：2003-07-04
申请号：KR1020010045693
申请日：2001-07-28
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L29/78615 , H01L29/78636
Abstract: An isolation layer (170) that is formed in a trench has an oxide liner and a nitride liner that are sequentially formed along surface of trench and dielectric layer that fills the trench. The trench has gate and drain/source regions having thickness less than or equal to that of a semiconductor layer. An independent claim is included for semiconductor device manufacturing method.
Abstract translation: 在沟槽中形成的隔离层（170）具有氧化物衬垫和氮化物衬垫，其沿着填充沟槽的沟槽和介电层的表面顺序地形成。 沟槽具有厚度小于或等于半导体层的栅极和漏极/源极区域。 包括半导体器件制造方法的独立权利要求。
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公开(公告)号：KR100840787B1
公开(公告)日：2008-06-23
申请号：KR1020070018200
申请日：2007-02-23
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L29/0847 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
Abstract: A semiconductor device and a manufacturing method thereof are provided to prevent a current crowding phenomenon at an edge of a drain region by forming a channel region with the same width as a source region. An active region is formed on a semiconductor substrate and includes a first impurity region, a second impurity region, and a channel region, which is formed between the first and second impurity regions. Field regions are formed on the semiconductor substrate to be partially overlapped with the first and second impurity regions, such that an active region is defined. A source region(600) is formed on the first impurity region with a first width. The source region is adjacent to the channel region. A drain region(700) is formed on the second impurity region width a second width and isolated from the channel region on the other side of the source region. A gate structure(500) is formed on the channel region.
Abstract translation: 提供半导体器件及其制造方法，通过形成与源极区域宽度相同的沟道区域来防止漏极区域的边缘处的电流拥挤现象。 有源区形成在半导体衬底上，并且包括形成在第一和第二杂质区之间的第一杂质区，第二杂质区和沟道区。 场区域形成在半导体衬底上以与第一和第二杂质区域部分重叠，从而限定有源区域。 源区域（600）以第一宽度形成在第一杂质区域上。 源极区域与沟道区域相邻。 漏区700在第二杂质区宽度上形成第二宽度，并与源极区另一侧的沟道区隔离。 栅极结构（500）形成在沟道区上。
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公开(公告)号：KR1020150015966A
公开(公告)日：2015-02-11
申请号：KR1020130092074
申请日：2013-08-02
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/66795 , H01L21/823431 , H01L21/8238 , H01L21/823821 , H01L27/0886 , H01L29/66787 , H01L29/66803 , H01L21/28273 , H01L21/28141 , H01L21/31051 , H01L21/76224 , H01L21/76256
Abstract: 본 발명은 제 1 영역과 제 2 영역을 포함하는 기판을 준비하고, 상기 제 1 영역 및 제 2 영역에 액티브 핀들을 형성하고, 상기 액티브 핀들과 교차하고, 상기 액티브 핀들의 측면들과 마주하는 면들을 가지는 게이트 전극들을 형성하고, 상기 액티브 핀들을 덮는 오즈(off-set zero) 절연막을 형성하고, 상기 제 1 영역을 덮는 제 1 잔류 식각 방지막 및 제 1 하드 마스크 패턴을 형성하고, 상기 제 2 영역의 액티브 핀들에 제 1 불순물을 주입하고, 상기 제 1 하드 마스크 패턴 및 제 1 잔류 식각 방지막을 제거하고, 제 2 영역을 덮는 제 2 잔류 식각 방지막 및 제 2 하드 마스크 패턴을 형성하고, 상기 제 1 영역의 액티브 핀에 제 2 불순물을 주입하고, 상기 제 2 잔류 식각 방지막 및 제 2 하드 마스크 패턴을 제거하는 것을 포함하는 반도체 소자의 제조방법이 제안된다.
Abstract translation: 本发明提出一种半导体器件的制造方法，包括： 准备包括第一和第二区域的基板的步骤; 在所述第一和第二区域中形成有效销的步骤; 形成与有源引脚交叉并具有与有效引脚的侧面相对的侧面的栅电极的步骤; 形成覆盖有源销的偏置零绝缘膜的步骤; 形成覆盖所述第一区域的第一残留蚀刻防止膜和第一硬掩模图案的步骤; 将第一异物注入到第二区域的活动销中的步骤; 消除第一硬掩模图案和第一残留蚀刻防止膜的步骤; 形成覆盖第二区域的第二残留蚀刻防止膜和第二硬掩模图案的步骤; 将第二异物注入到第一区域的活动销中的步骤; 以及消除第二残留蚀刻防止膜和第二硬掩模图案的步骤。 半导体器件的制造方法可以通过使用其中在离子注入过程中垂直分布良好的有机膜（硬掩模图案）来精确地限定位于深度位置的离子注入区域。
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公开(公告)号：KR100836767B1
公开(公告)日：2008-06-10
申请号：KR1020070011692
申请日：2007-02-05
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L29/1033 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
Abstract: A semiconductor device having a MOS transistor controlling a high voltage and a method for forming the semiconductor device are provided to increase a breakdown voltage of a high voltage MOS(Metal Oxide Semiconductor) transistor by minimizing a focusing of an electric field. A semiconductor device includes a field insulation film, a gate(116), a channel region, a highly doped region, and a lightly doped region(110a). The field insulation film defines first and second substrate regions. The gate is arranged to traverse over the first substrate region. The channel region is defined in the first substrate region under the gate and includes first and second portions. The first portion has a first width in a channel width direction. The second portion has a second width. The highly doped region is formed on the second substrate region. The lightly doped region is formed at one side of the channel region and encloses a side surface and a bottom surface of the highly doped region. The first portion is arranged between the second substrate region and the second portion. The first portion is close to the field insulation film between the first and second substrate regions. The first width is smaller than the second width.
Abstract translation: 提供具有控制高电压的MOS晶体管的半导体器件和用于形成半导体器件的方法，以通过最小化电场的聚焦来增加高压MOS（金属氧化物半导体）晶体管的击穿电压。 半导体器件包括场绝缘膜，栅极（116），沟道区，高掺杂区和轻掺杂区（110a）。 场绝缘膜限定第一和第二衬底区域。 栅极布置成在第一衬底区域上方遍历。 通道区域限定在栅极下方的第一衬底区域中，并且包括第一和第二部分。 第一部分具有在通道宽度方向上的第一宽度。 第二部分具有第二宽度。 高掺杂区域形成在第二衬底区域上。 轻掺杂区域形成在沟道区域的一侧并且包围高掺杂区域的侧表面和底表面。 第一部分布置在第二基板区域和第二部分之间。 第一部分靠近第一和第二基板区域之间的场绝缘膜。 第一宽度小于第二宽度。
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公开(公告)号：KR100402392B1
公开(公告)日：2003-10-17
申请号：KR1020010068820
申请日：2001-11-06
Applicant: 삼성전자주식회사
IPC: H01L21/762
CPC classification number: H01L21/76264 , H01L21/76283
Abstract: A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. The trench region has a deep trench region where the upper silicon layer penetrates to the buried insulating layer and a shallow trench region existing at an outside of the deep trench region. The method of forming a trench region with deep and shallow trench regions includes patterning an upper silicon layer of an SOI substrate. A trench oxide layer and a trench liner are conformally formed on a sidewall and a bottom of the trench region. The trench liner on the bottom of the trench region, the trench oxide layer, and the upper silicon layer are successively patterned to form the deep trench region where the buried insulating layer is exposed. The trench region existing at an outside of the deep trench region corresponds to the shallow trench region.
Abstract translation: 提供了一种具有沟槽隔离结构的半导体器件及其制造方法。 该器件具有沟槽区域和隔离结构。 沟槽区被设置为在SOI衬底的预定区域处限定有源区，该SOI衬底通过在衬底基板上顺序地堆叠埋入绝缘层和上硅层而形成。 隔离结构填充沟槽区域的内部。 沟槽区域具有深硅沟道区域，其中上硅层穿透到掩埋绝缘层，浅沟道区域存在于深沟沟道区域的外部。 形成具有深和浅沟槽区的沟槽区的方法包括图案化SOI衬底的上硅层。 沟槽氧化物层和沟槽衬垫共形地形成在沟槽区域的侧壁和底部上。 沟槽区域的底部上的沟槽衬垫，沟槽氧化物层和上部硅层依次图案化以形成暴露掩埋绝缘层的深沟槽区域。 存在于深沟槽区域外侧的沟槽区域对应于浅沟槽区域。
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Patent Agency Ranking
公开(公告)号：KR1020030010429A
公开(公告)日：2003-02-05
申请号：KR1020010045693
申请日：2001-07-28
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L29/78615 , H01L29/78636
Abstract: PURPOSE: An SOI(Silicon On Insulator) device having a trench isolation layer and a method for fabricating the same are provided to reduce junction capacitance of the SOI device by forming a structure of a dual trench having two regions of different depth. CONSTITUTION: A semiconductor substrate(130) including a base layer(110), a buried oxide layer(115), and a semiconductor layer(120) is prepared. A trench(T) having the first region and the second region is formed to define an active region of the semiconductor layer(120). The depth of the first region is less than the thickness of the semiconductor layer(120). The depth of the second region is equal to the thickness of the semiconductor layer(120). An isolation layer(170) is formed by stacking an oxide layer liner(155), a nitride layer liner(160), and an insulating layer(165) on an inner wall and a bottom of the trench(T).
Abstract translation: 目的：提供具有沟槽隔离层的SOI（绝缘体上硅）器件及其制造方法，以通过形成具有不同深度的两个区域的双沟槽的结构来减少SOI器件的结电容。 构成：制备包括基底层（110），掩埋氧化物层（115）和半导体层（120）的半导体衬底（130）。 形成具有第一区域和第二区域的沟槽（T），以限定半导体层（120）的有源区。 第一区域的深度小于半导体层（120）的厚度。 第二区域的深度等于半导体层（120）的厚度。 通过在沟槽（T）的内壁和底部堆叠氧化物层衬垫（155），氮化物层衬垫（160）和绝缘层（165）来形成隔离层（170）。
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公开(公告)号：KR1020160009753A
公开(公告)日：2016-01-27
申请号：KR1020140089745
申请日：2014-07-16
Applicant: 삼성전자주식회사
Inventor： 유승한
IPC: H01L21/027 , G03F7/20
CPC classification number: H01L21/306 , H01L21/3085 , H01L21/3086 , H01L21/823418 , H01L21/823431 , H01L21/823456 , H01L29/66553 , H01L21/0274
Abstract: 본발명의일 실시예에따른반도체소자의제조방법은이중패터닝공정을이용하여다양한폭의패턴들을형성하는것을포함한다.
Abstract translation: 根据本发明的实施例，半导体器件的制造方法包括使用双重图案化工艺形成具有各种宽度的图案。 半导体器件的制造方法包括：在基板上依次形成下层和上层; 在上层上形成第一牺牲图案和第二牺牲图案; 在所述第一牺牲图案的侧壁中形成第一间隔物，以及在所述第二牺牲图案的侧壁中形成第二间隔物; 选择性地去除所述第一牺牲图案和所述第二牺牲图案; 通过蚀刻暴露于第一间隔物和第二间隔物的上层来形成第一上图案和第二上图案; 通过去除第一间隔件和第二间隔件，暴露第一上图案的上表面和第二上图案的上表面; 在所述第二上部图案的侧壁中形成第三间隔物; 以及通过蚀刻暴露于第一上部图案的下层和通过蚀刻暴露于第二上部图案和第三间隔物的下层而形成宽度大于第一下部图案的宽度的第二下部图案来形成第一下部图案。
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公开(公告)号：KR100744139B1
公开(公告)日：2007-08-01
申请号：KR1020060058879
申请日：2006-06-28
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
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公开(公告)号：KR100546392B1
公开(公告)日：2006-01-26
申请号：KR1020030077188
申请日：2003-11-01
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/115 , H01L27/11526 , H01L27/11546
Abstract: 싱글폴리 OTP 셀에서 플로팅 게이트의 상면을 PEOX막으로 덮고 있는 EPROM 소자 및 이를 포함하는 반도체 소자와 그 제조 방법에 관하여 개시한다. 본 발명에 따른 반도체 소자는 OTP 셀 영역과 메인 칩 영역을 가지는 반도체 기판에서 OTP 셀 영역에 OTP 셀 트랜지스터를 구성하기 위하여 형성된 플로팅 게이트를 포함한다. 반도체 기판의 메인 칩 영역에는 트랜지스터를 구성하기 위한 게이트가 형성되어 있다. PEOX막이 OTP 셀 영역 및 메인 칩 영역에 걸쳐 연장되어 있으며, PEOX막은 상기 플로팅 게이트를 이에 근접한 상태에서 덮는 동시에 상기 게이트를 그와 소정 거리 이격된 상태에서 덮는다. 메인 칩 영역에서는 게이트와 PEOX막과의 사이에 SiON막이 개재되어 있다.
싱글 폴리OTP, 플로팅 게이트, PEOX, SiON, 데이터 리텐션-
公开(公告)号：KR102083493B1
公开(公告)日：2020-03-02
申请号：KR1020130092074
申请日：2013-08-02
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
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