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    비아가 수지 봉지 영역 내측에 형성된 ＰＢＧＡ 패키지용인쇄회로기판과 그를 이용한 ＰＢＧＡ 패키지
    2.
    发明公开
    비아가 수지 봉지 영역 내측에 형성된 ＰＢＧＡ 패키지용인쇄회로기판과 그를 이용한 ＰＢＧＡ 패키지 无效
    PBGA封装类型的印刷电路板通过形成在封装区域内的PBGA封装和使用该封装的PBGA封装

    公开(公告)号：KR1020070078231A

    公开(公告)日：2007-07-31

    申请号：KR1020060008301

    申请日：2006-01-26

    Applicant: 삼성전자주식회사

    Inventor： 김형욱 ,  목승곤 ,  윤한신

    IPC: H01L23/28

    CPC classification number: H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L23/481 ,  H01L23/293 ,  H01L23/31 ,  H01L24/26

    Abstract: A PCB(Printed Circuit Board) and a PBGA(Plastic Ball Grid Array) using the same are provided to prevent the generation of a cut portion between a circuit line pattern and a ball land in spite of the generation of delamination between the PCB and a resin sealing part using a via formed at an inner side of the resin sealing part. A PCB includes a chip mounting region(10) for mounting a semiconductor chip, a circuit line pattern(20) around the chip mounting region, a resin sealing region(50) at an upper portion, a plurality of ball lands for contacting the circuit line pattern at a lower portion, and a via. The via(30) is used for supplying an electrical connection path between the circuit line pattern and the ball land. The via is formed at an inner side of the resin sealing region.

    Abstract translation: 提供了使用其的PCB（印刷电路板）和PBGA（塑料球栅阵列），以防止在PCB和a之间产生分层而在电路线图案和球面之间产生切割部分 使用形成在树脂密封部的内侧的通孔的树脂密封部。 PCB包括用于安装半导体芯片的芯片安装区域（10），围绕芯片安装区域的电路线图案（20），在上部的树脂密封区域（50），用于接触电路 下部的线条图案和通孔。 通孔（30）用于在电路线图案和球面之间提供电连接路径。 通孔形成在树脂密封区域的内侧。

    반도체 패키지
    6.
    发明公开
    반도체 패키지 无效
    半导体封装

    公开(公告)号：KR1020130038581A

    公开(公告)日：2013-04-18

    申请号：KR1020110103017

    申请日：2011-10-10

    Applicant: 삼성전자주식회사

    Inventor： 노영훈 ,  윤한신 ,  김우재 ,  박성우

    IPC: H01L23/34

    CPC classification number: H01L24/97 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: PURPOSE: A semiconductor package is provided to dissipate the heat generated from a logic semiconductor chip using a heat radiation cap and to prevent performance degradation. CONSTITUTION: A memory chip(20) is adhered on a package substrate(10). A logic semiconductor chip(30) is adhered on the memory chip. A printed circuit board(23) includes a first pad(12) and a second pad(13). An inner solder ball(33) is arranged between the memory chip and the logic semiconductor chip. A heat radiation cap(43) covers the memory chip and the logic semiconductor chip. A heat transfer matter(41) is arranged between the heat radiation cap and the logic semiconductor chip.

    Abstract translation: 目的：提供半导体封装以消散使用散热帽从逻辑半导体芯片产生的热量并防止性能下降。 构成：存储芯片（20）粘附在封装衬底（10）上。 逻辑半导体芯片（30）粘附在存储器芯片上。 印刷电路板（23）包括第一焊盘（12）和第二焊盘（13）。 内部焊球（33）布置在存储芯片和逻辑半导体芯片之间。 散热帽（43）覆盖存储芯片和逻辑半导体芯片。 在散热帽和逻辑半导体芯片之间布置传热物质（41）。

    반도체 소자 패키지
    8.
    发明公开
    반도체 소자 패키지 无效
    半导体器件封装

    公开(公告)号：KR1020100010747A

    公开(公告)日：2010-02-02

    申请号：KR1020080071759

    申请日：2008-07-23

    Applicant: 삼성전자주식회사

    Inventor： 윤한신 ,  권영신

    IPC: H01L23/48 ,  H01L23/36

    CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: PURPOSE: A semiconductor device package is provided to improve the mechanical strength of a semiconductor package by forming a die pad and a lead pattern having a second thickness thicker than a first thickness. CONSTITUTION: A semiconductor chip(200) has a conducting pad. The die pad(102) has a top side(102a) and a bottom side facing with the top side. The die pad has an interval of first thickness between the top and bottom side. A lead pattern(104) comprises a second part having the second thickness(t2) thicker than the first thickness. A radiation member(300) comprises a groove arranged on the bottom side. A conductive line electrically interlinks a conductive pad with the lead pattern corresponded to the conducting pad.

    Abstract translation: 目的：提供半导体器件封装，通过形成具有比第一厚度厚的第二厚度的管芯焊盘和引线图案来提高半导体封装的机械强度。 构成：半导体芯片（200）具有导电焊盘。 管芯焊盘（102）具有顶侧（102a）和与顶侧相对的底侧。 管芯焊盘在顶部和底部之间具有第一厚度的间隔。 引线图案（104）包括具有比第一厚度厚的第二厚度（t2）的第二部分。 辐射构件（300）包括设置在底侧的凹槽。 导电线将导电焊盘与对应于导电焊盘的引线图案电连接。

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