公开(公告)号：KR1020090096887A

公开(公告)日：2009-09-15

申请号：KR1020080021967

申请日：2008-03-10

Applicant: 삼성전자주식회사

Inventor： 신동석 ,  김기철 ,  이정덕

IPC: H01L21/24

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843

Abstract: A semiconductor device having a metal silicide layer and a method of manufacturing the semiconductor device are provided to realize high integration and reliability by removing a sidewall pattern of the gate electrode completely and making a transistor having a stress layer effect. In a semiconductor device having a metal silicide layer and a method of manufacturing the semiconductor device, a gate electrode(125) is formed on a substrate(100). A stress concentration structure is formed from the center of side to lower part of the gate electrode and a multi-layer is formed. An impurity layer is formed on the substrate with being adjacent to the stress concentration structure, and a metal silicide layer(180) is formed within the impurity layer. The stress structure generates stress in lower part of side of the gate electrode, and the caused stress is concentrated on a channel region of the semiconductor device.

Abstract translation: 提供具有金属硅化物层的半导体器件和制造半导体器件的方法，以通过完全去除栅电极的侧壁图案并制造具有应力层效应的晶体管来实现高集成度和可靠性。 在具有金属硅化物层的半导体器件和制造半导体器件的方法中，在衬底（100）上形成栅电极（125）。 应力集中结构由栅电极的一侧到下部的中心形成，形成多层。 在衬底上形成与应力集中结构相邻的杂质层，在杂质层内形成金属硅化物层（180）。 应力结构在栅电极的下侧产生应力，并且引起的应力集中在半导体器件的沟道区域上。

公开(公告)号：KR101406226B1

公开(公告)日：2014-06-13

申请号：KR1020080042452

申请日：2008-05-07

Applicant: 삼성전자주식회사

Inventor： 이정훈 ,  신홍재 ,  남서우 ,  손세일 ,  김상두 ,  이정덕 ,  권상욱

IPC: H01L21/24 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7843

Abstract: 듀얼 실리사이드 및 듀얼 스트레스 라이너를 반도체 소자의 제조방법을 개시한다. 본 발명의 반도체 소자의 제조방법은 제1 MOS 영역과 상기 제1 MOS 영역과 반대 도전형의 제2 MOS 영역에 게이트 전극 및 소스/드레인 영역이 형성된 반도체 기판을 제공하는 단계; 상기 제1 MOS 영역을 노출시키면서 상기 제2 MOS 영역 위에 실리사이드 방지막을 형성하는 단계; 노출된 상기 제1 MOS 영역의 상기 게이트 전극 및 상기 소스/드레인 영역 위 제1 금속 실리사이드를 형성하고 상기 실리사이드 방지막을 제거하는 단계; 상기 제2 MOS 영역을 노출시키면서 상기 제1 금속 실리사이드가 형성된 상기 제1 MOS 영역 위에 제1 스트레스 라이너를 형성하는 단계; 노출된 상기 제2 MOS 영역의 상기 게이트 전극 및 상기 소스/드레인 영역 위 제2 금속 실리사이드를 형성하는 단계; 및 상기 제2 금속 실리사이드가 형성된 상기 제2 MOS 영역 위에 제2 스트레스 라이너를 형성하는 단계를 포함한다.
듀얼 실리사이드, 듀얼 스트레스 라이너, 실리사이드 방지막

公开(公告)号：KR101376260B1

公开(公告)日：2014-03-20

申请号：KR1020080034273

申请日：2008-04-14

Applicant: 삼성전자주식회사

Inventor： 선민철 ,  신동석 ,  이정덕

IPC: H01L21/335 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6656

Abstract: 반도체소자및 그제조방법이제공된다. 반도체소자는반도체기판, 반도체기판상에형성된게이트절연막, 게이트절연막상에형성된게이트전극, 게이트전극측벽에형성된제 1 스페이서, 제 1 스페이서에정렬되어반도체기판내에형성된소오스/드레인영역, 게이트전극및 소오스/드레인영역상면에형성된실리사이드막및 제 1 스페이서및 실리사이드막끝단부를덮는제 2 스페이서를포함한다.

公开(公告)号：KR1020090108917A

公开(公告)日：2009-10-19

申请号：KR1020080034273

申请日：2008-04-14

Applicant: 삼성전자주식회사

Inventor： 선민철 ,  신동석 ,  이정덕

IPC: H01L21/335 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6656

Abstract: PURPOSE: A semiconductor device is provided to prevent the performance degradation of the semiconductor device according to the reduction of the semiconductor device. CONSTITUTION: A semiconductor device includes a semiconductor substrate(200), a gate insulating layer(205), a gate electrode(210), the first spacer(242'), a source/drain region(224), a silicide film(255b), and the second spacer(260). The gate insulating layer is formed on the semiconductor substrate. The gate electrode is formed on the gate insulating layer. The first spacer is formed in the gate electrode side wall. The source/drain region is formed within the semiconductor substrate by arranging at the first spacer. The silicide film is created on the gate electrode and the source/drain region. The second spacers cover the first spacer and the end tip of silicide film.

Abstract translation: 目的：提供一种半导体器件，以根据半导体器件的减少来防止半导体器件的性能下降。 构成：半导体器件包括半导体衬底（200），栅极绝缘层（205），栅电极（210），第一间隔物（242'），源/漏区（224），硅化物膜 ）和第二间隔物（260）。 栅极绝缘层形成在半导体衬底上。 栅电极形成在栅绝缘层上。 第一间隔物形成在栅电极侧壁中。 源极/漏极区域通过在第一间隔物处布置而形成在半导体衬底内。 在栅极电极和源极/漏极区域上形成硅化物膜。 第二间隔物覆盖第一间隔物和硅化物膜的末端。

公开(公告)号：KR1020090032843A

公开(公告)日：2009-04-01

申请号：KR1020070098400

申请日：2007-09-28

Applicant: 삼성전자주식회사

Inventor： 김기철 ,  신홍재 ,  박문한 ,  이화성 ,  이정덕

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/20

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7849

Abstract: A MOS transistor and CMOS transistor having a strained channel epi layer and methods of fabricating the transistors are provided to reduce the process cost for growing the epi layer by selectively forming the channel epi layer inside the channel trench. An N active region and a P active region are limited on an NMOS region and a PMOS region by forming the device isolation structure on a substrate(100). A pad oxide film(121) and a hard mask film(123) are formed in the substrate. N channel trench is created in the N active region by selectively etching the N active region. Transformed N channel epi layer(131) is formed within the N channel trench. The P channel trench is created in the P active region by selectively etching the P active region. A transformed P-channel epi layer(141) is formed in the P channel trench. An N gate electrode and a P gate electrode are formed by etching back the gate conductive film.

Abstract translation: 提供具有应变通道外延层的MOS晶体管和CMOS晶体管以及制造晶体管的方法，以通过选择性地在通道沟槽内形成沟道外延层来降低生长外延层的工艺成本。 通过在衬底（100）上形成器件隔离结构，N个有源区和P有源区被限制在NMOS区和PMOS区上。 在衬底中形成衬垫氧化膜（121）和硬掩模膜（123）。 通过选择性地蚀刻N个有源区域，在N个有源区域中产生N沟道沟槽。 在N沟道沟槽内形成变换的N沟道外延层（131）。 通过选择性蚀刻P活性区域，在P活性区域中产生P沟槽沟槽。 在P沟道沟槽中形成变换的P沟道外延层（141）。 通过蚀刻栅极导电膜形成N栅电极和P栅电极。

公开(公告)号：KR1020090020847A

公开(公告)日：2009-02-27

申请号：KR1020070085456

申请日：2007-08-24

Applicant: 삼성전자주식회사

Inventor： 김기철 ,  신홍재 ,  이정덕

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/28044 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of manufacturing a MOS transistor having a strained channel and a MOS transistor manufactured thereby are provided to improve reliability of a semiconductor device by preventing short circuit between conductive films adjacent to a gate pattern. A gate pattern(120) is formed on a semiconductor substrate(100). The gate pattern comprises a gate electrode and a capping layer pattern which successively are laminated. In the capping layer pattern, the width of a lower capping film(114b) is narrower than the width of a top capping layer(116a). A spacer(134) covers the side wall of the gate pattern. By using a spacer and a gate pattern as an etching mask, the semiconductor board of both sides of the gate pattern is etched and the recess region is formed. The recess region is filled in with the semiconductor layer.

Abstract translation: 提供制造具有应变通道的MOS晶体管和由其制造的MOS晶体管的方法，以通过防止与栅极图案相邻的导电膜之间的短路来提高半导体器件的可靠性。 在半导体衬底（100）上形成栅极图案（120）。 栅极图案包括依次层叠的栅电极和覆盖层图案。 在封盖层图案中，下封盖膜（114b）的宽度比顶盖层（116a）的宽度窄。 间隔物（134）覆盖栅极图案的侧壁。 通过使用间隔物和栅极图案作为蚀刻掩模，蚀刻栅极图案的两侧的半导体板并形成凹部区域。 凹部区域被半导体层填充。

公开(公告)号：KR1020080056942A

公开(公告)日：2008-06-24

申请号：KR1020060130158

申请日：2006-12-19

Applicant: 삼성전자주식회사

Inventor： 김기철 ,  신동석 ,  이정덕

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/31053

Abstract: A trench isolation method of a semiconductor device is provided to completely cover the sidewalls of an active region by an upper isolation layer and a lower isolation layer by forming a lower isolation layer partially exposing the sidewalls of the active region and by forming an upper isolation layer on the lower isolation layer. A trench(31) is formed in a predetermined region of a semiconductor substrate(30) to confine an active region(40). A lower isolation layer(44) is formed which partially exposes the sidewall of the active region and fills the trench. An upper isolation layer is formed on the lower isolation layer, covering the exposed sidewall of the active region. The lower isolation layer can be composed of a trench oxide layer(36) covering the inner wall of the trench, a liner(38a) covering the trench oxide layer, and a gap-fill isolation layer(42a) filling the trench surrounded by the liner, wherein an etch process or a cleaning process can be performed on the upper surface of the active region.

Abstract translation: 提供了一种半导体器件的沟槽隔离方法，通过形成部分暴露有源区的侧壁的下隔离层和通过形成上隔离层来完全覆盖有源区的侧壁的上隔离层和下隔离层 在较低隔离层上。 沟槽（31）形成在半导体衬底（30）的预定区域中以限制有源区（40）。 形成下部隔离层（44），其部分地暴露有源区域的侧壁并填充沟槽。 上隔离层形成在下隔离层上，覆盖有源区的暴露的侧壁。 下隔离层可以由覆盖沟槽的内壁的沟槽氧化物层（36），覆盖沟槽氧化物层的衬垫（38a）和填充由沟槽氧化物层包围的沟槽的间隙填充隔离层（42a）组成 衬垫，其中可以在有源区域的上表面上执行蚀刻工艺或清洁工艺。

公开(公告)号：KR100782325B1

公开(公告)日：2007-12-06

申请号：KR1020060110948

申请日：2006-11-10

Applicant: 삼성전자주식회사

Inventor： 김기철 ,  이정덕

IPC: H01L21/027

CPC classification number: H01L21/0273 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method for manufacturing a semiconductor device is provided to compensate for photoresist patterns by adjusting the thickness of a polymer layer formed on a photoresist pattern based on the position of a to-be-etched layer. Photoresist patterns are formed on a to-be-etched layer(S11). By reacting selectively the photoresist patterns using reaction gas, a polymer layer having different thicknesses based on the position of the photoresist patterns is formed(S12). The to-be-etched layer is etched by using the photoresist patterns and the polymer layer as an etch mask(S13). The polymer layer having the different thicknesses has relatively thick portions on the photoresist patterns, which is positioned at an edge of the to-be-etched layer.

Abstract translation: 提供一种制造半导体器件的方法，用于通过基于待蚀刻层的位置调节形成在光刻胶图案上的聚合物层的厚度来补偿光刻胶图案。 在被蚀刻层上形成光刻胶图案（S11）。 通过使用反应气体选择性地使光致抗蚀剂图案反应，形成基于光致抗蚀剂图案的位置具有不同厚度的聚合物层（S12）。 通过使用光致抗蚀剂图案和聚合物层作为蚀刻掩模蚀刻被蚀刻的层（S13）。 具有不同厚度的聚合物层在光致抗蚀剂图案上具有相对较厚的部分，其位于被蚀刻层的边缘。

公开(公告)号：KR1020090116478A

公开(公告)日：2009-11-11

申请号：KR1020080042452

申请日：2008-05-07

Applicant: 삼성전자주식회사

Inventor： 이정훈 ,  신홍재 ,  남서우 ,  손세일 ,  김상두 ,  이정덕 ,  권상욱

IPC: H01L21/24 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7843

Abstract: PURPOSE: A fabrication method of a semiconductor device is provided to simplify a process and reduce time and costs by applying one of two silicide barriers to one dual stress liner. CONSTITUTION: In a fabrication method of a semiconductor device, a gate electrode(110) and source/drain regions(104,106) are formed on a first MOS area and a second MOS area opposite to the first MOS area. A silicide barrier is formed on the second MOS area while exposing the first MOS area. A first metal silicide(108) is formed on the gate electrode and a source/drain region of the first MOS area. A first stress(124) is formed on the first MOS area, and a second metal silicide is formed on a gate electrode and a source/drain region of an exposed second MOS area. A second stress liner(126) is formed on the second MOS area in which the second metal silicide is formed.

Abstract translation: 目的：提供半导体器件的制造方法，以通过将两个硅化物屏障中的一个施加到一个双重应力衬垫来简化工艺并减少时间和成本。 构成：在半导体器件的制造方法中，在与第一MOS区域相反的第一MOS区域和第二MOS区域上形成栅电极（110）和源极/漏极区域（104,106）。 在第二MOS区域上形成硅化物屏障，同时露出第一MOS区域。 第一金属硅化物（108）形成在栅极电极和第一MOS区域的源极/漏极区域上。 第一应力（124）形成在第一MOS区上，第二金属硅化物形成在暴露的第二MOS区的栅电极和源极/漏极区上。 在形成第二金属硅化物的第二MOS区上形成第二应力衬垫（126）。

公开(公告)号：KR1020090083654A

公开(公告)日：2009-08-04

申请号：KR1020080009588

申请日：2008-01-30

Applicant: 삼성전자주식회사

Inventor： 이정덕 ,  김기철

IPC: H01L21/24 ,  H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

Abstract: A transistor having metal silicide and method of manufacturing the same, method of manufacturing a semiconductor device using the same are provided to prevent production of the metal silicide residue in the spacer. The gate dielectric layer pattern(102) and polysilicon pattern(104a) are laminated on the single crystalline silicon substrate(100). The spacer(106a) is formed in the polysilicon pattern side wall. Impurity regions(108,110) are formed under the substrate surface of the polysilicon pattern. The first metal silicide pattern(114a) is formed on the substrate surface. The second metal silicide pattern(115) is formed at the upper part of the polysilicon pattern. The second metal silicide pattern has the narrow line width which is identical to the line width of the polysilicon pattern.

Abstract translation: 提供具有金属硅化物的晶体管及其制造方法，制造使用其的半导体器件的制造方法以防止间隔物中的金属硅化物残留物的产生。 栅电介质层图案（102）和多晶硅图案（104a）层压在单晶硅衬底（100）上。 间隔物（106a）形成在多晶硅图案侧壁中。 杂质区（108,110）形成在多晶硅图案的衬底表面下方。 第一金属硅化物图案（114a）形成在基板表面上。 第二金属硅化物图案（115）形成在多晶硅图案的上部。 第二金属硅化物图案具有与多晶硅图案的线宽度相同的窄线宽度。