公开(公告)号：KR20210027896A

公开(公告)日：2021-03-11

申请号：KR1020190108936A

申请日：2019-09-03

Applicant: 삼성전자주식회사

Inventor： 이준하 ,  이선규 ,  임정돈 ,  정병훈

IPC: G11C7/10 ,  H04L25/02

CPC classification number: H01L25/0657 ,  G11C7/1048 ,  G11C16/06 ,  G11C29/00 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1093 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/18 ,  H04L25/0278 ,  G11C2207/2254 ,  H01L2223/6611 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/14511 ,  H01L2924/15311

Abstract: 캘리브레이션 시간을 줄일 수 있는 멀티-칩 패키지 및 그것의 ZQ 캘리브레이션 방법이 개시된다. 멀티-칩 패키지의 마스터 칩에서 ZQ 저항을 이용하여 제1 ZQ 캘리브레이션 동작을 수행하고 나서, 나머지 슬레이브 칩들은 마스터 칩의 DQ 패드와 일대일 대응 관계에 기초하여, 마스터 칩의 DQ 패드의 터미네이션 저항값을 이용하여 슬레이브 칩들 각각의 DQ 패드들의 제2 ZQ 캘리브레이션 동작을 동시에 수행한다. 멀티-칩 패키지는 2번의 ZQ 캘리브레이션 동작들에 의해 ZQ 캘리브레이션을 완료하므로, 캘리브레이션 시간을 줄일 수 있다.

公开(公告)号：KR20210031278A

公开(公告)日：2021-03-19

申请号：KR1020190113036A

申请日：2019-09-11

Applicant: 삼성전자주식회사

Inventor： 신동호 ,  강경태 ,  이준하 ,  김동성 ,  이장우 ,  임정돈 ,  정병훈

IPC: G11C29/50 ,  G11C7/22

CPC classification number: G11C29/50012 ,  H03K3/017 ,  G11C7/22 ,  H03K19/21 ,  H03K5/24 ,  G11C2207/2254

Abstract: 본 개시에 따르면, 파라미터 모니터링 회로는, 제1 오프셋이 인가된 제1 코드 및 제2 오프셋이 인가된 제2 코드를 생성하도록 구성되는 코드 생성 회로, 코드 생성 회로에 의해 제공되는 제1 코드 및 제2 코드를 각각 파라미터에 적용함으로써 제1 파라미터 및 제2 파라미터를 생성하도록 구성되는 파라미터 조정 회로, 제1 파라미터에 대한 기준 파라미터 값과의 비교 결과를 나타내는 제1 비교 결과 및 제2 파라미터에 대한 기준 파라미터 값과의 비교 결과를 나타내는 제2 비교 결과를 생성하도록 구성되는 비교 회로 및 제1 비교 결과 및 제2 비교 결과를 기초로 파라미터의 에러를 검출하도록 구성되는 파라미터 에러 검출 회로를 포함할 수 있다.

公开(公告)号：KR1020030048949A

公开(公告)日：2003-06-25

申请号：KR1020010079004

申请日：2001-12-13

Applicant: 삼성전자주식회사

Inventor： 이준하

IPC: H01L21/336

Abstract: PURPOSE: A method for fabricating a semiconductor transistor is provided to prevent stress of a semiconductor substrate in a spacer formation process, and to make the impurities implanted into the semiconductor substrate not diffused to the outside by omitting a process for forming a spacer on a side of a gate electrode. CONSTITUTION: The gate electrode(34) of a reverse trapezoid type is formed on a semiconductor substrate(30). Impurity ions are implanted into the semiconductor substrate at a predetermined angle by using the gate electrode as a mask so that a low density source/drain region(36a,36b) is formed on a side of the gate electrode. Impurity ions are implanted into the low density source/drain region in a direction perpendicular to the gate electrode by using the gate electrode as a mask so that a high density source/drain region(38a,38b) is formed in the low density source/drain region.

Abstract translation: 目的：提供一种用于制造半导体晶体管的方法，以防止间隔物形成过程中的半导体衬底的应力，并且通过省略在侧面上形成间隔物的工艺，使得注入到半导体衬底中的杂质不会扩散到外部 的栅电极。 构成：在半导体衬底（30）上形成反梯形类型的栅电极（34）。 通过使用栅电极作为掩模将杂质离子以预定角度注入到半导体衬底中，使得在栅电极的一侧上形成低密度源/漏区（36a，36b）。 通过使用栅电极作为掩模，将杂质离子注入到与栅电极垂直的方向上的低密度源极/漏极区域中，使得在低密度源极/漏极区域中形成高密度源极/漏极区域（38a，38b） 漏区。

公开(公告)号：KR1020030049005A

公开(公告)日：2003-06-25

申请号：KR1020010079070

申请日：2001-12-13

Applicant: 삼성전자주식회사

Inventor： 이준하

IPC: H01L21/336

Abstract: PURPOSE: A method for fabricating a semiconductor transistor is provided to improve an operation characteristic of the semiconductor transistor by decreasing a resistance value of an impurity region while a high impurity density in the impurity region is maintained. CONSTITUTION: A gate electrode(34) is formed on a semiconductor substrate(10). The first spacer is formed on a side part of the gate electrode. Impurity ions are implanted into the semiconductor substrate at the first ion implantation angle with respect to the vertical surface of the semiconductor substrate by using the gate electrode including the first spacer as a mask so that a low density source/drain region(36a,36b) is formed at a side part of the gate electrode. The second spacer is formed at a side part of the first spacer. Impurity ions are implanted into the low density source/drain region at the second ion implantation angle with respect to the vertical surface of the semiconductor substrate by using the gate electrode including the second spacer as a mask. Impurity ions are implanted into the low density source/drain region in a direction perpendicular to the semiconductor substrate so that a high density source/drain region(44a,44b) is formed in the low density source/drain region.

Abstract translation: 目的：提供一种用于制造半导体晶体管的方法，通过降低杂质区域的电阻值，同时保持杂质区域中的高杂质浓度来改善半导体晶体管的操作特性。 构成：在半导体衬底（10）上形成栅电极（34）。 第一间隔物形成在栅电极的侧部上。 通过使用包括第一间隔物的栅电极作为掩模，以相对于半导体衬底的垂直表面的第一离子注入角度将杂质离子注入到半导体衬底中，使得低密度源极/漏极区域（36a，36b） 形成在栅电极的侧部。 第二间隔件形成在第一间隔件的侧部。 通过使用包括第二间隔物的栅电极作为掩模，将杂质离子以相对于半导体衬底的垂直表面的第二离子注入角度注入低密度源极/漏极区。 在垂直于半导体衬底的方向上将杂质离子注入低密度源极/漏极区域，使得在低密度源极/漏极区域形成高密度源极/漏极区域（44a，44b）。

公开(公告)号：KR1020170057917A

公开(公告)日：2017-05-26

申请号：KR1020150161263

申请日：2015-11-17

Applicant: 삼성전자주식회사

Inventor： 이준하 ,  현석훈 ,  배용철

IPC: H03K19/177

Abstract: 상기목적을달성하기위한본 발명의실시예에따른직렬화기는제 1 논리회로, 제 2 논리회로, 귀환회로를포함할수 있다. 제 1 논리회로는복수의입력신호를제공받아제 1 출력신호를생성할수 있다. 제 2 논리회로는복수의입력신호를제공받아제 1 출력신호와상보적인제 2 출력신호를생성할수 있다. 귀환회로는제 1 출력신호와제 2 출력신호를제공받아제 1 출력신호와제 2 출력신호의전환타이밍을보정할수 있다.

Abstract translation: 根据本发明的一个方面，提供了一种串行器，包括第一逻辑电路，第二逻辑电路和反馈电路。 第一逻辑电路可通过接收多个输入信号来产生第一输出信号。 第二逻辑电路可以接收多个输入信号以生成与第一输出信号互补的第二输出信号。 反馈电路可以接收第一输出信号和第二输出信号并且校正第一输出信号和第二输出信号的切换时刻。

公开(公告)号：KR1020010068316A

公开(公告)日：2001-07-23

申请号：KR1020000000171

申请日：2000-01-04

Applicant: 삼성전자주식회사

Inventor： 이준하

IPC: H01L21/336

Abstract: PURPOSE: A method for manufacturing a MOS transistor is provided to improve a characteristic of a transistor by minimizing a backward short-channel effect of the transistor. CONSTITUTION: A gate insulating layer(6) and a gate electrode(8) are formed on a semiconductor substrate(2). Dopant ions are implanted on the semiconductor substrate(2) in order to form a source/drain region(14). The implanted ions are activated by performing a thermal process for the semiconductor substrate(2). The source/drain region(14) is formed thereby. The dopant ions are implanted on the semiconductor substrate(2) in order to form a doped region(16). The doped region(16) is used for controlling a threshold voltage of a channel region.

Abstract translation: 目的：提供一种用于制造MOS晶体管的方法，通过最小化晶体管的反向短沟道效应来改善晶体管的特性。 构成：在半导体衬底（2）上形成栅极绝缘层（6）和栅电极（8）。 掺杂离子注入到半导体衬底（2）上以形成源/漏区（14）。 通过对半导体衬底（2）执行热处理来激活注入的离子。 由此形成源/漏区（14）。 掺杂剂离子注入到半导体衬底（2）上以便形成掺杂区域（16）。 掺杂区域（16）用于控制沟道区域的阈值电压。

公开(公告)号：KR1020000073363A

公开(公告)日：2000-12-05

申请号：KR1019990016609

申请日：1999-05-10

Applicant: 삼성전자주식회사

Inventor： 이준하

IPC: H01L21/66

Abstract: PURPOSE: A simulation method is to simulate an ion injection and a diffusion of indium impurities by using a conventional simulation unit while establishing various models and parameters regarding indium. CONSTITUTION: Indium ions are injected into a wafer, and a first ion injection depth is measured. Nine moments are drawn out from the measurement result by using a dual pearson ion injection model equation. A diffusion process is performed regarding the wafer, and a second ion injection depth is measured. An optimum value of the moment parameter regarding impurity diffusivity of indium is calculated by using the moment parameter and the measured data. A parameter regarding a pair reaction of the indium impurities, a diffusivity of an indium interstitial pair and a solid solubility are established. A segregation value and a transport value are optimized in an interface between the wafer and the oxidation layer. More than a MOSFET(Metal Oxide Semiconductor Field Effect Transistor) device is selected to establish a process condition with a simulation input file, and a function of a gate length and a threshold voltage is calculated. The function of respective gate lengths and threshold voltages is calculated while varying the process condition in the input file. A relative absolute error of the calculated function value is to be checked to converge into a predetermined scope. When the error exceeds the predetermined scope, the pair reaction parameter is changed. A minimum parameter is selected if the error exceeds the scope again.

Abstract translation: 目的：模拟方法是通过使用传统的模拟单元模拟铟杂质的离子注入和扩散，同时建立关于铟的各种模型和参数。 构成：将铟离子注入晶片，并测量第一离子注入深度。 通过使用双Pearson离子注入模型方程从测量结果中抽出九个时刻。 对晶片执行扩散处理，并测量第二离子注入深度。 通过使用力矩参数和测量数据计算关于铟杂质扩散率的力矩参数的最佳值。 建立了关于铟杂质的对反应，铟间隙对的扩散性和固溶度的参数。 在晶片和氧化层之间的界面中优化偏析值和传输值。 选择MOSFET（金属氧化物半导体场效应晶体管）器件以建立具有模拟输入文件的工艺条件，并计算栅极长度和阈值电压的函数。 在改变输入文件中的处理条件的同时计算各个栅极长度和阈值电压的功能。 要检查计算的功能值的相对绝对误差以收敛到预定范围。 当误差超过预定范围时，改变对反应参数。 如果错误超出范围，则选择最小参数。

公开(公告)号：KR1020010086858A

公开(公告)日：2001-09-15

申请号：KR1020000010781

申请日：2000-03-03

Applicant: 삼성전자주식회사

Inventor： 이준하

IPC: H01L21/66

Abstract: PURPOSE: An optimizing method of a P-channel MOS(metal oxide semiconductor) transistor is to prevent boron of a gate electrode from being permeated into a channel region through a gate insulating film. CONSTITUTION: It determines a variation of a threshold voltage of a P-channel MOS transistor. If the variation of the threshold voltage is above a predetermined value, parameters related to boron permeation is analyzed through the first simulation. According to the analyzed result, a process optimizing condition for restraining the boron permeation is set. It determines whether phenomenon of boron permeation is happened by executing the second simulation applied with the process optimizing condition. As the result of the second simulation, if the phenomenon of boron permeation is not restrained, the first simulation is again executed. The parameter includes a dispersion coefficient of boron depending upon a grain size of material of a gate electrode, a dispersion coefficient of boron depending upon a thickness a gate insulating film, and a dispersion coefficient of boron depending upon a hydrogen concentration.

Abstract translation: 目的：P沟道MOS（金属氧化物半导体）晶体管的优化方法是防止栅电极的硼通过栅极绝缘膜渗入沟道区。 构成：它确定P沟道MOS晶体管的阈值电压的变化。 如果阈值电压的变化高于预定值，则通过第一次模拟分析与硼渗透相关的参数。 根据分析结果，设定了抑制硼渗透的工艺优化条件。 它通过执行使用过程优化条件的第二次模拟来确定硼渗透现象是否发生。 作为第二次模拟的结果，如果硼渗透现象不被抑制，则再次执行第一次模拟。 该参数包括取决于栅极材料的晶粒尺寸的硼的分散系数，取决于栅极绝缘膜的厚度的硼的分散系数和取决于氢浓度的硼的分散系数。