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公开(公告)号：KR1020160004176A
公开(公告)日：2016-01-12
申请号：KR1020140104540
申请日：2014-08-12
Applicant: 삼성전자주식회사
IPC: G06F1/00
CPC classification number: G11C5/14 , G06K19/07732 , G06K19/07743 , G11C5/06 , G11C5/063 , G11C7/10 , G11C7/22 , H01R12/73 , H01R13/6683
Abstract: 본발명은메모리카드및 이를포함하는전자시스템에관한것으로서, 더욱구체적으로는 2 쌍의대향하는가장자리들을갖는기판; 상기기판의삽입측가장자리(edge)에인접하여배열되고제 1 전압의전원단자를포함하는복수의제 1 열단자들; 및상기제 1 열단자들보다상기삽입측가장자리로부터이격되어배열되고제 2 전압의전원단자를포함하는복수의제 2 열단자들을갖는메모리카드가제공된다. 본발명은면적의활용을극대화하고전기적으로도안정적인전원공급이가능한메모리카드를제공할수 있다.
Abstract translation: 本发明涉及存储卡和包括该存储卡的电子系统。 更具体地，存储卡包括具有彼此面对的两对边缘的基板; 多个第一列端子，其与基板的插入部分的边缘相邻并且包括第一电压的电源端子; 以及与第一列端子相比与插入部的边缘分离的第二列端子，并且包括第二电压的电源端子。 根据本发明的存储卡可以最大限度地利用面积并提供稳定的功率。
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公开(公告)号：KR1020160004175A
公开(公告)日：2016-01-12
申请号：KR1020140104173
申请日：2014-08-12
Applicant: 삼성전자주식회사
IPC: G06F1/00
CPC classification number: G11C5/14 , G06K19/07732 , G06K19/07743 , G11C5/06 , G11C5/063 , G11C7/10 , G11C7/22 , H01R12/73 , H01R13/6683
Abstract: 본발명은메모리카드및 이를포함하는전자시스템에관한것으로서, 더욱구체적으로는 2 쌍의대향하는가장자리들을갖는기판; 상기기판의삽입측가장자리(edge)에인접하여배열되고제 1 전압의전원단자를포함하는복수의제 1 열단자들; 및상기제 1 열단자들보다상기삽입측가장자리로부터이격되어배열되고제 2 전압의전원단자를포함하는복수의제 2 열단자들을갖는메모리카드가제공된다. 본발명은면적의활용을극대화하고전기적으로도안정적인전원공급이가능한메모리카드를제공할수 있다.
Abstract translation: 本发明涉及存储卡和包括该存储卡的电子系统。 更具体地，存储卡包括具有彼此面对的两对边缘的基板; 第一列端子，其与衬底的插入部分的边缘相邻并且包括第一电压的电源端子; 以及与第一列端子相比与插入部的边缘分离的第二列端子，并且包括第二电压的电源端子。 本发明可以提供使区域的使用最大化并且提供电稳定功率的存储卡。
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Patent Agency Ranking
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公开(公告)号：KR1020100129600A
公开(公告)日：2010-12-09
申请号：KR1020090048246
申请日：2009-06-01
Applicant: 삼성전자주식회사
Inventor： 임광만
CPC classification number: G11C5/025 , G11C5/04 , H01L23/60 , H01L2924/0002 , H05K1/0259 , H01L2924/00
Abstract: PURPOSE: A semiconductor device and a data memory device including the same are provided to efficiently protect a semiconductor device from electrostatic discharge by electrically connecting a protection pattern to a ground terminal only when a voltage applied to a substrate is out of a preset voltage range. CONSTITUTION: A ground terminal(106) is formed on a first substrate. A first protection pattern is formed on the first substrate. A switching element(110) is serially connected between the ground terminal and the first protection pattern. Two ground terminals are formed on one side of the first substrate.
Abstract translation: 目的：提供半导体器件和包括该半导体器件的数据存储器件，仅当施加到衬底的电压超出预设电压范围时，通过将保护图案电连接到接地端子来有效地保护半导体器件免受静电放电。 构成：在第一基板上形成接地端子（106）。 在第一基板上形成第一保护图案。 开关元件（110）串联连接在接地端子和第一保护图案之间。 两个接地端子形成在第一基板的一侧上。
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公开(公告)号：KR1020080070991A
公开(公告)日：2008-08-01
申请号：KR1020070009000
申请日：2007-01-29
Applicant: 삼성전자주식회사
Inventor： 임광만
CPC classification number: H01L23/3135 , H01L23/3121 , H01L24/48 , H01L25/16 , H01L2224/05553 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2924/00014 , H01L2924/15192 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H05K1/023 , H05K3/284 , H05K2201/10636 , H05K2203/049 , H05K2203/1322 , Y02P70/611 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor module, a module substrate, and a manufacturing method thereof are provided to protect passive elements in a manufacturing process by using an antistatic layer. A plurality of passive elements(54) are mounted on a substrate(50). A semiconductor chip(52) is mounted on the substrate and is electrically connected to the passive elements. An antistatic layer(70) is formed to cover the passive elements. An encapsulant layer is formed to cover the passive elements and the semiconductor chip. At least one of the passive elements is composed of a capacitor. The capacitor is covered with the antistatic layer. A part of the passive elements is covered with the antistatic layer.
Abstract translation: 提供半导体模块，模块基板及其制造方法，以通过使用抗静电层来保护制造工艺中的无源元件。 多个无源元件（54）安装在基板（50）上。 半导体芯片（52）安装在基板上并与无源元件电连接。 形成防静电层（70）以覆盖被动元件。 形成封装层以覆盖无源元件和半导体芯片。 无源元件中的至少一个由电容器组成。 电容器被抗静电层覆盖。 被动元件的一部分被抗静电层覆盖。
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公开(公告)号：KR100817072B1
公开(公告)日：2008-03-26
申请号：KR1020060107942
申请日：2006-11-02
Applicant: 삼성전자주식회사
Inventor： 임광만
IPC: H01L25/10
CPC classification number: G06F13/385
Abstract: A memory card is provided to independently use a controller and a memory package by inserting a memory package into an adaptor. A controller(110) for controlling the operation of a card(100) is built in an adaptor(150). A memory package(130) outside of the adaptor is inserted into the adaptor, electrically connected to the controller. The controller varies with the kind of the card. The adaptor can include a first recognition pattern to be electrically connected to the memory package. The position and shape of the first recognition pattern can be determined according to the kind of the card.
Abstract translation: 提供存储卡以通过将存储器包插入适配器来独立地使用控制器和存储器包。 用于控制卡（100）的操作的控制器（110）内置在适配器（150）中。 适配器外部的存储器包（130）被插入到适配器中，电连接到控制器。 控制器根据卡的种类而变化。 适配器可以包括要电连接到存储器包的第一识别图案。 可以根据卡的种类来确定第一识别图案的位置和形状。
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公开(公告)号：KR1020070105553A
公开(公告)日：2007-10-31
申请号：KR1020060037808
申请日：2006-04-26
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L25/105 , H01L23/13 , H01L24/13 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06586 , H01L2225/1023 , H01L2225/1052 , H01L2225/1088 , H01L2924/00014 , H01L2924/14 , H01L2924/15159 , H01L2924/15311 , H01L2924/1815 , H01L2924/19107 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
Abstract: A package-on-package structure is provided to reduce a degree of warpage and to reduce the number of bumps by connecting electrically a first and second packages through wires. A first semiconductor chip(115) includes a plurality of first internal terminals(134) and a plurality of first external terminals(136) and is disposed on a first substrate(110). A second semiconductor chip(125) includes a plurality of second internal terminals(144) and a plurality of second external terminals(146) and is disposed on a second substrate. A connective structure(200) is formed to connect at least one of the first external terminals to at least one of the second external terminals. The first semiconductor chip is connected through a first bonding unit(132) to the first internal terminals of the first substrate. The second semiconductor chip is connected through a second bonding unit(142) to the second internal terminals of the second substrate. The first bonding unit is a wire bonding structure or a solder bump structure. The second bonding unit is formed with one of the wire bonding structure or the solder bump structure.
Abstract translation: 提供了一种封装封装结构，以通过电线将第一和第二封装电连接，以减少翘曲程度并减少凸块的数量。 第一半导体芯片（115）包括多个第一内部端子（134）和多个第一外部端子（136），并且设置在第一基板（110）上。 第二半导体芯片（125）包括多个第二内部端子（144）和多个第二外部端子（146），并且设置在第二基板上。 连接结构（200）被形成为将至少一个第一外部端子连接到第二外部端子中的至少一个。 第一半导体芯片通过第一接合单元（132）连接到第一基板的第一内部端子。 第二半导体芯片通过第二接合单元（142）连接到第二基板的第二内部端子。 第一接合单元是引线接合结构或焊料凸块结构。 第二接合单元由引线键合结构或焊料凸块结构之一形成。
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