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公开(公告)号：KR101274202B1
公开(公告)日：2013-06-14
申请号：KR1020070132683
申请日：2007-12-17
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
Abstract: 웰전위제어용콘택을가지는 NAND 플래시메모리소자에관하여개시한다. 본발명에따른 NAND 플래시메모리소자는기판에서제1 방향으로연장되어있고제1 웰이형성되어있는라인형상의복수의활성영역과, 복수의활성영역에교차하도록제1 웰위에서제2 방향으로연장되어있는한 쌍의더미워드라인을포함한다. 한쌍의더미워드라인은상호소정거리만큼이격되어있는제1 더미워드라인및 제2 더미워드라인으로이루어진다. 제1 더미워드라인및 제2 더미워드라인에는항상 0 V의바이어스전압이인가되는상태로유지되어, 복수의활성영역중 제1 더미워드라인및 제2 더미워드라인사이에위치되는부분은그 활성영역의다른부분과는전기적으로독립되어있다. 상기제1 더미워드라인과제2 더미워드라인과의사이에위치되는활성영역에는제1 웰에웰 바이어스전압을인가하기위한바이어스인가용콘택이형성되어있다.
Abstract translation: NAND闪速存储器件包括在衬底上沿第一方向延伸的多个有源区，所述有源区包括第一导电的第一阱，在与第一阱垂直的第二方向上在第一阱上延伸的多个字线 方向，第一和第二虚拟字线在第一阱上沿第二方向延伸，第一和第二虚拟字线彼此分离以限定它们之间的中间区域，第一和第二虚拟字线适于接收基本上 约0V的恒定偏置电压，以及在第一和第二伪字线之间的中间区域中的有源区域中的至少一个触点。
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公开(公告)号：KR101192359B1
公开(公告)日：2012-10-18
申请号：KR1020070132606
申请日：2007-12-17
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L23/48 , G11C5/063 , G11C16/0483 , H01L21/02697 , H01L21/0337 , H01L21/32139 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L2924/0002 , H01L2924/00
Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction
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公开(公告)号：KR1020090065207A
公开(公告)日：2009-06-22
申请号：KR1020070132683
申请日：2007-12-17
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/10891 , H01L27/2463
Abstract: A NAND flash memory device having a contact for controlling electric potential of a well is provided to maintain an electrically dependent state of a second well part of active regions without removing an unnecessary part by a trimming process. A plurality of active areas having a line shape is extended in a first direction on a substrate. A first well of a first conductive type is formed on the active areas. A plurality of word lines(120) are extended in a second direction perpendicular to the first direction on the first well in order to cross the active regions in order to form a plurality of memory cells. A pair of dummy word lines are maintained in a bias voltage state of 0V. A contact for applying a bias is formed between a first dummy word line(140A) and a second dummy word line(140B) in the partial active region which is selected from the active regions. The contact is formed to apply a well bias voltage to the first well.
Abstract translation: 提供具有用于控制阱的电位的触点的NAND快闪存储器件，以保持活性区域的第二阱部分的电依赖状态，而不需要通过修整过程去除不需要的部分。 具有线状的多个有源区域在基板上沿第一方向延伸。 第一导电类型的第一阱形成在有源区上。 多个字线（120）在垂直于第一阱上的第一方向的第二方向上延伸以跨过有源区域以形成多个存储单元。 一对虚拟字线保持在0V的偏置电压状态。 在从有源区域中选择的部分有源区域中的第一虚拟字线（140A）和第二虚拟字线（140B）之间形成用于施加偏压的触点。 形成接触以向第一阱施加阱偏置电压。
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公开(公告)号：KR101654693B1
公开(公告)日：2016-09-06
申请号：KR1020150186763
申请日：2015-12-24
Applicant: 삼성전자주식회사
IPC: H01L21/027 , H01L21/768 , H01L27/02 , H01L27/06 , H01L27/115
Abstract: 본발명은콘택플러그가전기적으로연결되는라인패턴의옆에더미부를포함하는다른라인패턴을형성하여높은집적도를가지면서도충분한공정마진을확보할수 있고신뢰성있는연결을제공할수 있는반도체소자및 메모리소자를제공한다. 본발명의일 측면에따른반도체소자는, 제 1 방향으로연장된제 1 라인패턴, 상기제 1 라인패턴에이격하여상기제 1 방향으로연장되며, 서로전기적으로절연되고동일한폭을갖는더미부와연결부를포함하는제 2 라인패턴, 상기제 2 라인패턴의상기더미부에인접하여형성되며, 적어도상기제 1 라인패턴과는전기적으로연결되는제 1 콘택플러그, 상기제 2 라인패턴의상기연결부와전기적으로연결되는제 2 콘택플러그및 상기제 1 라인패턴을중심으로상기제 2 라인패턴의반대쪽에서상기제 1 라인패턴에인접하여상기제 1 방향으로연장되며, 서로전기적으로절연되고동일한폭을갖는더미부와연결부를포함하는제 3 라인패턴을포함하고, 상기제 3 라인패턴의상기더미부는상기제 1 라인패턴을중심으로상기제 2 라인패턴의상기더미부의맞은편에형성되는것을특징으로한다.
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公开(公告)号：KR1020160004255A
公开(公告)日：2016-01-12
申请号：KR1020150186763
申请日：2015-12-24
Applicant: 삼성전자주식회사
IPC: H01L21/027 , H01L21/768 , H01L27/02 , H01L27/06 , H01L27/115
Abstract: 본발명은콘택플러그가전기적으로연결되는라인패턴의옆에더미부를포함하는다른라인패턴을형성하여높은집적도를가지면서도충분한공정마진을확보할수 있고신뢰성있는연결을제공할수 있는반도체소자및 메모리소자를제공한다. 본발명의일 측면에따른반도체소자는, 제 1 방향으로연장된제 1 라인패턴, 상기제 1 라인패턴에이격하여상기제 1 방향으로연장되며, 서로전기적으로절연되고동일한폭을갖는더미부와연결부를포함하는제 2 라인패턴, 상기제 2 라인패턴의상기더미부에인접하여형성되며, 적어도상기제 1 라인패턴과는전기적으로연결되는제 1 콘택플러그, 상기제 2 라인패턴의상기연결부와전기적으로연결되는제 2 콘택플러그및 상기제 1 라인패턴을중심으로상기제 2 라인패턴의반대쪽에서상기제 1 라인패턴에인접하여상기제 1 방향으로연장되며, 서로전기적으로절연되고동일한폭을갖는더미부와연결부를포함하는제 3 라인패턴을포함하고, 상기제 3 라인패턴의상기더미부는상기제 1 라인패턴을중심으로상기제 2 라인패턴의상기더미부의맞은편에형성되는것을특징으로한다.
Abstract translation: 本发明提供一种半导体器件和存储器件，其能够通过在电连接到接触插塞的不同线路图案旁边形成包括虚拟部分的线图案，从而确保足够的加工余量并提供可靠性的连接，同时具有高集成度。 根据本发明的一个方面的半导体器件包括：沿第一方向延伸的第一线图案; 第二线图形，其沿第一方向延伸以与第一线图案分离，并且包括虚拟部分和彼此电绝缘并具有相同宽度的连接部分; 第一接触插塞，其形成为与第二线路图案的虚拟部分相邻，并且至少与第一线路图案电连接; 第二接触插塞，其电连接到第二线路图形的连接部分; 以及第三线图案，其相对于第一线图案在第二线图案的相对侧上在第一方向上延伸为与第一线图案相邻，并且包括虚拟部分和与每个图案电绝缘的连接部分 其他并且具有相同的宽度。 第三线图案的虚拟部分相对于第一线图案形成在第二线图案的虚拟部分的相对侧上。
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Patent Agency Ranking
公开(公告)号：KR1020100083581A
公开(公告)日：2010-07-22
申请号：KR1020090003039
申请日：2009-01-14
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32139 , G03F7/70466 , G03F7/70475
Abstract: PURPOSE: A method for forming a semiconductor device is provided to form a fine pattern of the semiconductor device by using a damascene process and double patterning technique. CONSTITUTION: A second material layer pattern is formed on a first material layer. Space patterns are formed on the sidewall of the second material layer patterns. The second material layer patterns are removed. First material layer patterns(200a) are formed by etching the first material layer exposed by the spacer patterns. Third material layer patterns(600) filling the trenches delimited by the first material layer patterns are formed.
Abstract translation: 目的：提供一种用于形成半导体器件的方法，以通过使用镶嵌工艺和双重图案化技术形成半导体器件的精细图案。 构成：在第一材料层上形成第二材料层图案。 空间图案形成在第二材料层图案的侧壁上。 去除第二材料层图案。 通过蚀刻由间隔物图案暴露的第一材料层形成第一材料层图案（200a）。 形成填充由第一材料层图案限定的沟槽的第三材料层图案（600）。
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公开(公告)号：KR1020110002261A
公开(公告)日：2011-01-07
申请号：KR1020090059764
申请日：2009-07-01
Applicant: 삼성전자주식회사
IPC: H01L21/027 , H01L21/768
CPC classification number: H01L23/522 , H01L21/76816 , H01L23/5226 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11565 , H01L27/11568 , H01L2924/0002 , G03F7/70475 , H01L2924/00
Abstract: PURPOSE: A semiconductor device including the dummy is provided to obtain enough process margin with high integrity by implementing line pattern set having different line pattern including a dummy part near the line pattern. CONSTITUTION: A first line pattern is formed by expanding in a first direction on a semiconductor substrate(41). A second line pattern including the dummy part and the connection part is formed being distanced from the first line pattern. A first contact plug(27) is formed near the dummy part of the second line pattern.
Abstract translation: 目的：提供一种包括虚拟装置的半导体装置，通过实现具有不同线条图案的线条图案集合，以获得足够的具有高完整性的工艺余量，包括线图案附近的虚拟部分。 构成：通过在半导体衬底（41）上沿第一方向扩展形成第一线图案。 形成包括虚拟部分和连接部分的第二线条图形，其与第一线条图案相距离。 在第二线图案的虚拟部分附近形成第一接触插塞（27）。
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公开(公告)号：KR1020090081876A
公开(公告)日：2009-07-29
申请号：KR1020080008027
申请日：2008-01-25
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247 , H01L21/28
CPC classification number: H01L27/2463 , H01L21/28273 , H01L21/76897 , H01L27/10885
Abstract: A layout of a NAND flash memory for forming a connection pad using a self alignment double patterning is provided to simplify a trimming process and to reduce an error of pattern formation. A layout of a NAND flash memory is used for the self alignment double patterning process. The layout of the NAND flash memory includes a cell area, a peripheral circuit area, and a connection area between the cell area and the peripheral circuit area. The connection area includes a connection pattern(40). The connection pattern includes a plurality of first connection patterns(41) and second connection patterns(42). The plurality of first connection patterns progress to a first direction. The second connection pattern is positioned between the first connection patterns by the self alignment. The second connection pattern includes a connection pad(42a) which is arranged in plural rows to the second direction. The connection pad in the same row is arranged in the second connection pattern every other pad. The end of the second connection pattern is extended to the same position to the first direction.
Abstract translation: 提供了用于使用自对准双重图案形成连接焊盘的NAND快闪存储器的布局，以简化修整过程并减少图案形成的误差。 NAND闪存的布局用于自对准双重图案化处理。 NAND闪存的布局包括单元区域，外围电路区域以及单元区域和外围电路区域之间的连接区域。 连接区域包括连接图案（40）。 连接图案包括多个第一连接图案（41）和第二连接图案（42）。 多个第一连接图案进行到第一方向。 第二连接图案通过自对准位于第一连接图案之间。 第二连接图案包括沿第二方向布置成多行的连接垫（42a）。 同一行中的连接焊盘以每隔一个焊盘布置在第二连接图案中。 第二连接图案的端部延伸到与第一方向相同的位置。
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公开(公告)号：KR1020090065148A
公开(公告)日：2009-06-22
申请号：KR1020070132606
申请日：2007-12-17
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L23/48 , G11C5/063 , G11C16/0483 , H01L21/02697 , H01L21/0337 , H01L21/32139 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L2924/0002 , H01L27/10882 , H01L2924/00
Abstract: A NAND flash memory device and a manufacturing method thereof are provided to form constantly a channel length and to control constantly a critical voltage in each of memory cells by maintaining a uniform critical dimension in a fine mask pattern forming process for etching a conductive layer. A plurality of conductive lines(312) are formed in a first direction on an upper surface of a semiconductor board. The conductive lines are parallel to each other. A plurality of contact pads and the conductive lines are formed with one body at one end of the conductive lines in order to connect the conductive lines with an external circuit. A plurality of dummy conductive lines are extended from the contact pads to a second direction different from the direction. The dummy conductive lines have different lengths.
Abstract translation: 提供NAND闪速存储器件及其制造方法，以恒定地形成通道长度，并且通过在用于蚀刻导电层的精细掩模图案形成工艺中保持均匀的临界尺寸来恒定地控制每个存储器单元中的临界电压。 多个导电线（312）在半导体基板的上表面上沿第一方向形成。 导线彼此平行。 为了将导线与外部电路连接，多个接触焊盘和导线在导电线的一端形成有一个主体。 多个虚设导线从接触焊盘延伸到与该方向不同的第二方向。 虚拟导电线具有不同的长度。
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公开(公告)号：KR1020090054296A
公开(公告)日：2009-05-29
申请号：KR1020070121084
申请日：2007-11-26
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/0271 , G03F7/70466 , H01L21/32139
Abstract: 본 발명의 반도체 소자의 패턴 형성 방법은 기판 상에 제1 방향으로 반복적으로 형성되고 제1 방향과 수직인 제2 방향의 일단부가 제1 방향으로 동일하지 않는 복수의 제1 패턴들을 형성하는 것을 포함한다. 제1 패턴들중 상호 인접한 두 개의 제1 패턴들 사이에 셀프 얼라인 방식에 의해 상기 제1 방향으로 반복적으로 형성되는 복수의 제2 패턴들을 형성한다. 제1 패턴 및 제2 패턴의 일단부는 제1 방향으로 서로 정렬되도록 형성한다.
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