公开(公告)号：KR1020110004649A

公开(公告)日：2011-01-14

申请号：KR1020090062190

申请日：2009-07-08

Applicant: 삼성전자주식회사

Inventor： 김병술 ,  박광원 ,  이학용 ,  임주연

IPC: H01L23/12

CPC classification number: G11C5/14 ,  G11C5/04 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: A multi-chip system is provided to prevent the generation of malfunctions due to a peak current by preventing power voltages from being simultaneously supplied. CONSTITUTION: A plurality of chips(12_1 to 12_N) are prepared in a stacked structure. The chips have a slave-master relationship. A plurality of power voltages(Vcc1 to VccN) is inputted from the outside. The power voltages are supplied to the chips according to a pre-determined order using a power order controller. The power order controller delays at least one supply of the power voltages.

Abstract translation: 目的：提供多芯片系统，通过防止同时提供电源电压，防止由峰值电流引起的故障。 构成：以堆叠结构制备多个芯片（12_1至12_N）。 这些芯片具有从属关系。 从外部输入多个电源电压（Vcc1〜VccN）。 使用电源控制器根据预定的顺序将电源电压提供给芯片。 功率指令控制器延迟至少一个电源电压。