칩 스케일 렌즈를 포함한 발광장치
    1.
    发明公开
    칩 스케일 렌즈를 포함한 발광장치 审中-实审
    包括芯片级透镜的发光器件

    公开(公告)号:KR1020170125653A

    公开(公告)日:2017-11-15

    申请号:KR1020160055764

    申请日:2016-05-04

    CPC classification number: H01L33/60 H01L33/44 H01L33/507

    Abstract: 본발명의기술적사상에의한발광장치는제1 도전형반도체층, 활성층 및제2 도전형 반도체층이적층된발광적층체에상기제1 도전형반도체층과전기적으로연결된제1 전극층및 상기제2 도전형반도체층과전기적으로연결된제2 전극층구비하는발광구조, 상기발광구조상에배치된렌즈, 및, 상기렌즈상에배치된반사막을포함하는포함하는것을특징으로한다

    Abstract translation: 一英尺平方值是第一导电类型半导体层,有源层mitje第二导电类型半导体层,其中,所述层叠发光层压在所述第一导电型半导体层和第一电极层电连接到与本发明的技术特征的第二导电 型的特征在于,它包括:包括半导体层和第二电发光结构,发光结构布置在光透镜,而且,设置在所述电极层上形成反射膜被连接到具有透镜

    발광소자 어레이 및 이를 이용한 발광소자 패키지
    3.
    发明公开
    발광소자 어레이 및 이를 이용한 발광소자 패키지 审中-实审
    发光器件阵列和发光器件封装

    公开(公告)号:KR1020130087160A

    公开(公告)日:2013-08-06

    申请号:KR1020120008226

    申请日:2012-01-27

    Abstract: PURPOSE: A light emitting device array and a light emitting device package are provided to implement uniform brightness and to reduce a dark part between chips by using a plurality of light emitting devices which are integrally connected to a sapphire substrate. CONSTITUTION: A plurality of light emitting devices (121-124) are integrally connected to a sapphire substrate (110). The light emitting devices include first semiconductor layers (121a), active layers (121b), and second semiconductor layers (121c). The light emitting devices include isolation areas (130) formed by an etching process. First electrodes (121d) are formed on the exposed first semiconductor layers. Second electrodes (121e) are formed on the second semiconductor layers.

    Abstract translation: 目的:提供一种发光器件阵列和发光器件封装,以通过使用与蓝宝石衬底整体连接的多个发光器件来实现均匀的亮度并减少芯片之间的暗部分。 构成:多个发光器件(121-124)与蓝宝石衬底(110)整体连接。 发光器件包括第一半导体层(121a),有源层(121b)和第二半导体层(121c)。 发光器件包括通过蚀刻工艺形成的隔离区域(130)。 第一电极(121d)形成在暴露的第一半导体层上。 第二电极(121e)形成在第二半导体层上。

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