公开(公告)号：KR1020090040050A

公开(公告)日：2009-04-23

申请号：KR1020070105618

申请日：2007-10-19

Applicant: 삼성전자주식회사

Inventor： 정재교 ,  이주범 ,  김도형 ,  김형수

IPC: H01L21/28

CPC classification number: H01L21/76834 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76837 ,  H01L27/10855

Abstract: A method for manufacturing a semiconductor device is provided to prevent the diffusion of the oxygen from an interlayer dielectric layer while forming the interlayer dielectric layer using TOSZ by applying an oxide preventing layer and a spacer as a dual oxidation preventing structure for a conductive wiring. A first interlayer dielectric layer(110) is formed on a substrate(100) with a contact region. Conductive wirings are formed on the first interlayer dielectric layer. The spacer is formed on the side walls of conductive wirings. An oxidation preventing layer(140) is formed on the first interlayer dielectric layer and the conductive wirings. A second interlayer dielectric layer(145) is formed on the oxidation preventing layer. The oxidation preventing layer is formed by using HDP-CVD oxide. The second interlayer dielectric layer is formed by using the TOSZ(ploysilasane).

Abstract translation: 提供了一种用于制造半导体器件的方法，以在通过施加氧化物防止层和间隔物作为导电布线的双重氧化防止结构的同时使用TOSZ形成层间电介质层的同时，防止来自层间电介质层的氧的扩散。 在具有接触区域的基板（100）上形成第一层间介质层（110）。 在第一层间电介质层上形成导电布线。 间隔件形成在导电布线的侧壁上。 在第一层间电介质层和导电布线上形成氧化防止层（140）。 在氧化防止层上形成第二层间介质层（145）。 通过使用HDP-CVD氧化物形成氧化防止层。 通过使用TOSZ（有机硅烷）形成第二层间电介质层。

公开(公告)号：KR1020080072296A

公开(公告)日：2008-08-06

申请号：KR1020070010823

申请日：2007-02-02

Applicant: 삼성전자주식회사

Inventor： 김도형 ,  김신혜 ,  이주범 ,  박민영 ,  정재교 ,  송흥섭

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/06 ,  H01L21/02362 ,  H01L21/76256 ,  H01L45/143 ,  H01L45/144

Abstract: A method of manufacturing a phase change memory device is provided to prevent an interface of a phase change material film pattern from being contaminated by forming first and second capping films on the phase change material film pattern. An insulation film pattern(130) having an opening is formed on a substrate(100). Lower electrodes(140) for burying the opening are formed. A phase change material film pattern(150) and an upper electrode film pattern(160), which is connected to the lower electrodes, are laminated in a structure. A first capping film(190) is formed along a surface of the insulation film pattern of the structure. A second capping film(200) covers the first capping film, such that a void is generated between the structures.

Abstract translation: 提供一种制造相变存储器件的方法，用于通过在相变材料膜图案上形成第一和第二封盖膜来防止相变材料膜图案的界面被污染。 在衬底（100）上形成具有开口的绝缘膜图案（130）。 形成用于埋入开口的下电极（140）。 以与该下电极连接的相变材料膜图案（150）和上部电极膜图案（160）层叠而成。 沿着结构的绝缘膜图案的表面形成第一覆盖膜（190）。 第二封盖膜（200）覆盖第一封盖膜，使得在结构之间产生空隙。

公开(公告)号：KR1020080071345A

公开(公告)日：2008-08-04

申请号：KR1020070009471

申请日：2007-01-30

Applicant: 삼성전자주식회사

Inventor： 장경태 ,  이주범 ,  김도형 ,  정재교 ,  송흥섭 ,  이미영

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor device having an etch-stop layer and a manufacturing method thereof are provided to improve a space margin of an opening by forming a residual etch-stop layer pattern on a bottom surface and a sidewall of the opening. A plurality of parallel gate patterns are formed across an upper surface of a semiconductor substrate(10). A plurality of openings are formed in regions between the gate patterns. Spacers are formed to cover sidewalls of the gate patterns. An impurity ion region is formed by implanting impurity ions into the semiconductor substrate having the spacers. An etch stop layer(64) is formed on the substrate having the impurity region. A carbon-containing layer(67) is formed on the substrate including the etch stop layer. A carbon-containing layer pattern is formed by etching back the carbon-containing layer. An etch stop layer is etched by using the carbon-containing layer pattern as a mask. The carbon-containing layer pattern is removed.

Abstract translation: 提供具有蚀刻停止层及其制造方法的半导体器件，以通过在开口的底表面和侧壁上形成残留的蚀刻停止层图案来改善开口的空间裕度。 在半导体衬底（10）的上表面上形成多个平行栅极图案。 在栅极图案之间的区域中形成多个开口。 隔板形成为覆盖栅极图案的侧壁。 通过将杂质离子注入到具有间隔物的半导体衬底中来形成杂质离子区域。 在具有杂质区域的衬底上形成蚀刻停止层（64）。 在包括蚀刻停止层的基板上形成含碳层（67）。 通过对含碳层进行回蚀而形成含碳层图案。 通过使用含碳层图案作为掩模蚀刻蚀刻停止层。 除去含碳层图案。

公开(公告)号：KR100829611B1

公开(公告)日：2008-05-14

申请号：KR1020060110918

申请日：2006-11-10

Applicant: 삼성전자주식회사

Inventor： 장경태 ,  이주범 ,  정재교 ,  송흥섭 ,  이미영

IPC: H01L21/8244 ,  H01L27/11

CPC classification number: H01L27/0688 ,  H01L27/088

Abstract: A stack type semiconductor device and a manufacturing method thereof are provided to maintain insulation property between a node contact plug and a word line by preventing a metal material from permeating from the node contact plug to a void. A first gate(30) is formed on a substrate. A first interlayer dielectric(50) is formed on the substrate to cover the first gate. A first active pattern(65) is formed on a portion of the first interlayer dielectric to penetrate the first interlayer dielectric, and is contacted with a portion of the substrate. A second gate(74) is formed on the first active pattern and the first interlayer dielectric. A buffer film(150) is formed on the first active pattern and the first interlayer dielectric to cover the second gate. A second interlayer dielectric(90) is formed on the buffer film. A node contact plug(170) penetrates the first and second interlayer dielectrics and the buffer film and is contacted with a portion of the substrate. The buffer film insulates the second gate from the node contact plug.

Abstract translation: 提供堆叠型半导体器件及其制造方法，通过防止金属材料从节点接触插塞渗透到空隙中，以保持节点接触插塞与字线之间的绝缘性。 第一栅极（30）形成在基板上。 在基板上形成第一层间电介质（50）以覆盖第一栅极。 第一有源图案（65）形成在第一层间电介质的一部分上以穿透第一层间电介质，并与衬底的一部分接触。 第二栅极（74）形成在第一有源图案和第一层间电介质上。 在第一有源图案和第一层间电介质上形成缓冲膜（150）以覆盖第二栅极。 在缓冲膜上形成第二层间电介质（90）。 节点接触插塞（170）穿透第一和第二层间电介质和缓冲膜并与衬底的一部分接触。 缓冲膜将第二栅极与节点接触插塞绝缘。

公开(公告)号：KR100843245B1

公开(公告)日：2008-07-02

申请号：KR1020070042116

申请日：2007-04-30

Applicant: 삼성전자주식회사

Inventor： 장경태 ,  이주범 ,  정재교 ,  송흥섭 ,  이미영

IPC: H01L21/027

CPC classification number: H01L21/0274 ,  G03F7/2022 ,  G03F7/70466

Abstract: A method for manufacturing a semiconductor device is provided to form a fine pattern through a double patterning process for reducing load of a photolithography process. A first pattern of a first material layer having a first width is formed on a target layer(22). A second pattern(24b) of the first material layer having a second width smaller than the first width is formed by oxidizing the first pattern of the first material layer. A first pattern(25) of a first oxide layer is formed around the second pattern of the first material layer. A third pattern of the first material layer is formed to fill up a gap between the first patterns of the first oxide layer and to cover the first patterns of the first oxide layer. The third pattern of the first material layer and the first pattern of the first oxide layer are planarized to expose the upper surface of the second pattern of the first material layer and to form a fourth pattern of the first material layer and a second pattern of the first oxide layer. The second pattern of the first oxide layer is removed. An etch process is performed to etch the target layer exposed by the second pattern of the first material layer and the fourth pattern of the first material layer.

Abstract translation: 提供一种用于制造半导体器件的方法，以通过双重图案化工艺形成精细图案，以减少光刻工艺的负载。 在目标层（22）上形成具有第一宽度的第一材料层的第一图案。 通过氧化第一材料层的第一图案，形成具有小于第一宽度的第二宽度的第一材料层的第二图案（24b）。 围绕第一材料层的第二图案形成第一氧化物层的第一图案（25）。 形成第一材料层的第三图案以填充第一氧化物层的第一图案之间的间隙并覆盖第一氧化物层的第一图案。 将第一材料层的第三图案和第一氧化物层的第一图案平坦化以暴露第一材料层的第二图案的上表面并形成第一材料层的第四图案，并且形成第二图案的第二图案 第一氧化物层。 去除第一氧化物层的第二图案。 执行蚀刻处理以蚀刻由第一材料层的第二图案和第一材料层的第四图案暴露的目标层。

公开(公告)号：KR1020090011246A

公开(公告)日：2009-02-02

申请号：KR1020070074643

申请日：2007-07-25

Applicant: 삼성전자주식회사

Inventor： 이미영 ,  장경태 ,  정재교

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/308

Abstract: A manufacturing method of semiconductor device is provided to improve reliability of a semiconductor device by forming a device isolation film with gap fill without a void. A trench is formed on a substrate(100) which on an etching stop pattern(200) is formed. A hole is formed on a top of the trench by forming a first isolation film(300) on the trench and the etching stop pattern. A buffer layer is formed on the first isolation film in order to fill the hole. The first isolation film on the etching stop pattern is exposed. A part of the buffer layer is removed. An exposed first isolation film is removed. A residual buffer layer(400a) filling a part of the hole is removed. A device isolation film is formed by forming a second isolation film on the first isolation film.

Abstract translation: 提供半导体器件的制造方法，以通过形成具有间隙填充的器件隔离膜而没有空隙来提高半导体器件的可靠性。 在形成有蚀刻停止图案（200）的基板（100）上形成沟槽。 通过在沟槽和蚀刻停止图案上形成第一隔离膜（300），在沟槽的顶部形成孔。 为了填充孔，在第一隔离膜上形成缓冲层。 蚀刻停止图案上的第一隔离膜被暴露。 缓冲层的一部分被去除。 去除暴露的第一隔离膜。 去除填充孔的一部分的残留缓冲层（400a）。 通过在第一隔离膜上形成第二隔离膜来形成器件隔离膜。

公开(公告)号：KR1020090003703A

公开(公告)日：2009-01-12

申请号：KR1020070066606

申请日：2007-07-03

Applicant: 삼성전자주식회사

Inventor： 장경태 ,  이주범 ,  정재교 ,  송흥섭 ,  이미영

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/306

Abstract: The method of manufacturing the semiconductor device is provided to form the degradation prevention layer on the high dielectric capacitor without the cracks and to improve the property of the electrical property of the capacitor. The contact areas(110,120) are formed in the substrate(100). The bottom electrode(170) is electrically connected to the contact area. The ferroelectric layer pattern(175) is formed on the bottom electrode. The upper electrode(180) is formed in the ferroelectric layer pattern. The surface of the high dielectric capacitor is plasma-processed. The degradation prevention layer(160) is formed on the high dielectric capacitor. The plasma processing is performed by using the oxygen or the ozone plasma. The degradation prevention layer is made of the metal oxide. The degradation prevention layer has the thickness of 50Å or 250Å.

Abstract translation: 提供了制造半导体器件的方法，以在高介电电容器上形成防腐蚀层，而没有裂纹，并提高了电容器的电性能。 接触区域（110,120）形成在基板（100）中。 底部电极（170）电连接到接触区域。 铁电层图案（175）形成在底部电极上。 上电极（180）形成为铁电层图案。 高介电电容的表面被等离子体处理。 降解防止层（160）形成在高介电电容器上。 通过使用氧气或臭氧等离子体进行等离子体处理。 防腐层由金属氧化物构成。 防腐层的厚度为50埃或250埃。