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公开(公告)号：KR1020120097862A
公开(公告)日：2012-09-05
申请号：KR1020110017363
申请日：2011-02-25
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F2212/7201 , G06F2212/7208 , Y02D10/13
Abstract: PURPOSE: A data storage system and data mapping method thereof are provided to reduce power consumption by dynamically controlling the number of non-volatile memories according to a host request. CONSTITUTION: NVM(Non-Volatile Memories)(200) store data inputted by a host. A controller(300) controls active channels for the NVM based on a host request and add the NVM corresponding to the active channels to a candidate mapping area list. The controller successively inputs data inputted from the host to an active area listed on the candidate mapping area list. The number of inactive channels is controlled based on a reference range.
Abstract translation: 目的：提供数据存储系统及其数据映射方法，通过根据主机请求动态控制非易失性存储器的数量来降低功耗。 构成：NVM（非易失性存储器）（200）存储由主机输入的数据。 控制器（300）基于主机请求控制NVM的活动通道，并将与活动通道相对应的NVM添加到候选映射区域列表。 控制器将从主机输入的数据连续地输入到候选映射区域列表中列出的有效区域。 基于参考范围来控制不活动通道的数量。
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公开(公告)号：KR1020110058575A
公开(公告)日：2011-06-01
申请号：KR1020090115414
申请日：2009-11-26
Applicant: 삼성전자주식회사
CPC classification number: G06F13/405
Abstract: PURPOSE: A bandwidth synchronization circuit and bandwidth synchronization method thereof in a data processing system are provided to improve the operation performance of SOC(System-On-Chip) and to reduce a manufacturing cost of the data processing system by minimizing synchronization bottleneck between a CPU and a bus. CONSTITUTION: An upsizer(200) is composed of a synchronizing packer and a sync unpaker according to processor clock. A synchronizing down unit(250) is connected to the upsizer in response to the bus clock of low frequency. The synchronizing packer performs synchronization packing about a write address, data, and response channel. The synchronizing packer performs synchronization packing about a read address and data channel.
Abstract translation: 目的：提供数据处理系统中的带宽同步电路和带宽同步方法，以提高SOC（片上系统）的运行性能，并通过最小化数据处理系统的同步瓶颈来降低数据处理系统的制造成本 和一辆公共汽车。 构成：根据处理器时钟，升压器（200）由同步封隔器和同步打包器组成。 响应于低频的总线时钟，同步下降单元（250）连接到升压器。 同步封隔器对写入地址，数据和响应通道执行同步打包。 同步打包器对读地址和数据通道执行同步打包。
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公开(公告)号：KR101282963B1
公开(公告)日：2013-07-08
申请号：KR1020060043080
申请日：2006-05-12
Applicant: 삼성전자주식회사
CPC classification number: G06F17/5027 , G01R31/31704
Abstract: 여기에 개시된 에뮬레이션 시스템은 검증 및 디버깅 프로그램을 저장하는 제 1 메모리; 상기 검증 및 디버깅 프로그램을 수행하는 프로세서; 상기 프로세서의 제어에 응답해서 상기 설계회로의 기능 검증 및 디버깅을 수행하는 에뮬레이터; 그리고 상기 에뮬레이터에서 수행된 기능 검증 및 디버깅의 결과를 저장하는 제 2 메모리를 포함하며, 상기 에뮬레이터는 상기 기능 검증 결과 발생된 상기 설계회로의 저장체들의 상태값과 넷들의 상태값을 추출하여 내부에 저장하고, 상기 내부에 저장된 상태값을 상기 제 2 메모리 및 상기 에뮬레이터의 입력으로 피드백하며, 상기 내부에 저장된 상태값은 상기 디버깅 동작시 외부로부터 인가된 수정 데이터에 의해 갱신되고, 상기 갱신된 상태값은 상기 제 2 메모리로 제공함과 동시에 상기 에뮬레이터의 입력으로 피드백된다.
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Patent Agency Ranking
公开(公告)号：KR1020130076430A
公开(公告)日：2013-07-08
申请号：KR1020110145017
申请日：2011-12-28
Applicant: 삼성전자주식회사
CPC classification number: G06F11/10 , G06F11/1008 , G06F12/00 , G06F12/0246 , G06F2212/7205
Abstract: PURPOSE: An adaptive copy-back method and a storage device using the same are provided to reduce the performance degradation of the storage device by performing copy-back operation by using adaptively using external and internal copy-back methods. CONSTITUTION: A memory device (230) includes page storage areas and temporarily stores data read from a source page in a page buffer and a buffer memory (220) temporarily stores the data. A memory controller (210) processes the error correction of data outputted from the page buffer to store the same in the buffer memory. The memory controller selectively executes an external copy-back process using the data or an internal copy-back process not using the data based on the number of bits corrected per unit data size. [Reference numerals] (100) Host device; (210) Memory controller; (220) Buffer memory; (230) Memory device
Abstract translation: 目的：提供一种自适应复制方法和使用该方法的存储设备，通过使用外部和内部复制方式自适应执行复制操作来减少存储设备的性能下降。 构成：存储装置（230）包括页面存储区域并临时存储从页面缓冲器中的源页面读取的数据和缓冲存储器（220）临时存储数据。 存储器控制器（210）处理从页面缓冲器输出的数据的错误校正，以将其存储在缓冲存储器中。 存储器控制器基于每单位数据大小校正的位数，使用数据或不使用数据的内部复制处理来选择性地执行外部复制处理。 （附图标记）（100）主机设备; （210）内存控制器; （220）缓冲存储器; （230）存储设备
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公开(公告)号：KR1020120046461A
公开(公告)日：2012-05-10
申请号：KR1020100108125
申请日：2010-11-02
Applicant: 삼성전자주식회사
CPC classification number: G06F13/4027
Abstract: PURPOSE: An interface device and a system including the same are provided to reduce latency and overhead of an interface device in the connection of a master device and a slave device. CONSTITUTION: A TMU(Transaction Management Unit)(210) partitions transaction into head sub-transactions from at least one master device. A buffer unit(230) stores one or more sub-transaction. A selecting circuit(240) selects the head sub-transaction and output of the buffer unit in response to a selection control signal.
Abstract translation: 目的：提供一种接口设备和包括该接口设备的系统，以减少接口设备在主设备和从设备的连接中的等待时间和开销。 构成：TMU（事务管理单元）（210）将事务从至少一个主设备分配到头部子事务中。 缓冲单元（230）存储一个或多个子事务。 选择电路（240）响应于选择控制信号选择缓冲单元的头部子交易和输出。
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公开(公告)号：KR101205325B1
公开(公告)日：2012-11-29
申请号：KR1020060043082
申请日：2006-05-12
Applicant: 삼성전자주식회사
CPC classification number: G06F17/5022
Abstract: 여기에 개시된 시뮬레이션(Simulation) 시스템은 시뮬레이션 시스템 외부로부터 입력된 검증 프로그램을 이용하여 설계 회로에 대한 시뮬레이션을 수행하는 프로세서; 그리고 상기 시뮬레이션이 수행되는 동안 상기 프로세서에 의해 처리된 상기 설계회로의 복수의 스토리지들의 상태값과 상기 설계회로에 대응되는 분할된 세그멘트를 저장하는 메모리를 포함하며, 상기 프로세서는 상기 분할된 세그멘트를 상기 복수의 스토리지들에 대응되는 가상 입출력 인터페이스로 갖는 분할된 세그멘트들을 재구성하여 상기 메모리에 저장하고, 상기 메모리에 저장된 상기 복수의 스토리지들의 상태값을 상기 메모리에 저장된 상기 분할된 세그멘트들의 입력값 또는 출력값으로 대체하고, 상기 대체된 입력값 또는 출력값을 이용하여 상기 설계회로에 대한 디버깅을 수행한다.
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公开(公告)号：KR1020070110168A
公开(公告)日：2007-11-16
申请号：KR1020060043082
申请日：2006-05-12
Applicant: 삼성전자주식회사
CPC classification number: G06F17/5022
Abstract: The present invention provides the simulation system and method thereof to reduce simulation and debugging time before layout wiring of a design circuit and after the same, and the distributed simulation system and method thereof to apply to power simulation to predict power consumption of a design circuit. A simulation system(100) includes a processor(30) simulating a design circuit(900) by using a verification program inputted from the outside of the simulation system, and a memory(50) which stores a partitioned segment corresponded to the design circuit and state value of plural storages(91) of the design circuit processed by the processor while the simulation runs. The processor reorganizes partitioned segments which have the partitioned segments as the virtual input and output interface corresponded to the plural storages, and stores them in a memory. The state values of the plural storages saved in the memory is replaced with input or output values of the partitioned segments saved in the memory. By using the replaced input or output values, the processor performs debugging for the design circuit.
Abstract translation: 本发明提供了一种在设计电路布线之前减少仿真和调试时间的仿真系统及其方法，其分布式仿真系统及其方法应用于功率仿真以预测设计电路的功耗。 模拟系统（100）包括通过使用从模拟系统的外部输入的验证程序来模拟设计电路（900）的处理器（30）和存储与设计电路相对应的分割段的存储器（50），以及 在模拟运行时由处理器处理的设计电路的多个存储器（91）的状态值。 处理器重组具有分割段的分区段，因为虚拟输入和输出接口对应于多个存储器，并将它们存储在存储器中。 保存在存储器中的多个存储器的状态值被保存在存储器中的分割段的输入或输出值代替。 通过使用替换的输入或输出值，处理器对设计电路执行调试。
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公开(公告)号：KR1020070110167A
公开(公告)日：2007-11-16
申请号：KR1020060043080
申请日：2006-05-12
Applicant: 삼성전자주식회사
CPC classification number: G06F17/5027 , G01R31/31704
Abstract: An emulation system and method thereof is provided to extract and check the state value of flip-flop in real-time, perform verification of a design circuit effectively with small memory resources, and reduce verification time and debugging time of a design circuit. The emulation system(1000) includes the followings: the first memory(400) which stores a verification and debugging program(210, 220); a processor(300) which runs the verification and debugging program; an emulator(100) performs verification and debugging of the above design circuit(90) in response to the control of the processor; and the second memory(400) which stores a result of verification and debugging. The above emulator extracts state values of the above design circuit generated as a result of the verification, and stores the result in the inside. The above emulator feeds back the state values saved in the inside into the second memory and the emulator input. State values saved in the inside are renewed by modified data coming from the outside while the above debugging works. The renewed state values are provided to the second memory as well as are fed back into input of the emulator at the same time.
Abstract translation: 提供了一种仿真系统及其实时方法来提取和检查触发器的状态值，以较小的存储资源有效地执行设计电路的验证，并减少了设计电路的验证时间和调试时间。 仿真系统（1000）包括以下内容：存储验证和调试程序（210,220）的第一存储器（400） 运行验证和调试程序的处理器（300）; 仿真器（100）响应于处理器的控制执行上述设计电路（90）的验证和调试; 以及存储验证和调试结果的第二存储器（400）。 上述仿真器提取作为验证结果生成的上述设计电路的状态值，并将结果存储在内部。 上述仿真器将内部保存的状态值反馈到第二个存储器和仿真器输入。 保存在内部的状态值在上述调试工作时通过来自外部的修改数据更新。 更新的状态值被提供给第二存储器，并且同时被反馈到仿真器的输入。
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