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公开(公告)号：KR102014118B1
公开(公告)日：2019-08-26
申请号：KR1020120116572
申请日：2012-10-19
Applicant: 삼성전자주식회사
IPC: H04L12/801 , H04L12/28
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公开(公告)号：KR101842245B1
公开(公告)日：2018-03-26
申请号：KR1020110073401
申请日：2011-07-25
Applicant: 삼성전자주식회사
CPC classification number: G06F13/4291 , G06F1/10 , G06F1/3237 , G06F13/28 , G06F13/364 , G06F13/405 , G06F13/4054 , G06F2213/0038 , Y02B70/12 , Y02B70/123 , Y02D10/128 , Y02D10/151
Abstract: 시스템온 칩버스장치및 그에따른루트클럭게이팅방법이개시된다. 그러한시스템온 칩버스장치는, 버스와클럭게이팅부를포함한다. 상기버스는시스템온 칩의 IP들과같은기능블록들사이를연결한다. 상기클럭게이팅부는상기버스의인터페이스부에연결되며, 상기버스에설치된버스브릿지장치의동작에사용되는클럭을트랜잭션검출신호의상태에따라근본적으로게이팅한다. 따라서, 트랜잭션의검출신호의상태에따라클럭이버스장치에공급되거나차단되므로전력소모가최소화또는감소된다.
Abstract translation: 公开了片上系统总线设备和根时钟门控方法。 这种片上系统总线设备包括总线和时钟门控部分。 总线连接功能块，如片上系统的IP。 时钟门控单元连接到总线的接口单元，并且根据事务检测信号的状态基本上控制用于安装在总线中的总线桥单元的操作的时钟。 因此，根据交易的检测信号的状态，时钟被提供给总线设备或从总线设备阻断，因此功耗被最小化或减小。
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公开(公告)号：KR1020140050318A
公开(公告)日：2014-04-29
申请号：KR1020120116572
申请日：2012-10-19
Applicant: 삼성전자주식회사
IPC: H04L12/801 , H04L12/28
CPC classification number: H04L47/125 , H04L25/14 , H04L49/109
Abstract: A channel management method for transmitting first to third channel packets among five channel packets of an advanced extensible interface (AXI) to a backbone channel comprises a step of dividing the backbone channel into first and second sub-channels; a step of transmitting the first channel packet through the first sub-channel; a step of transmitting the second channel packet through the second sub-channel; and a step of transmitting the third channel packet through the backbone channel.
Abstract translation: 一种用于将高级可扩展接口（AXI）的五个信道分组中的第一到第三信道分组发送到骨干信道的信道管理方法包括将骨干信道划分为第一和第二子信道的步骤; 通过第一子信道发送第一信道分组的步骤; 通过第二子信道发送第二信道分组的步骤; 以及通过骨干信道发送第三信道分组的步骤。
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公开(公告)号：KR1020120041008A
公开(公告)日：2012-04-30
申请号：KR1020100102557
申请日：2010-10-20
Applicant: 삼성전자주식회사
CPC classification number: G06F13/4027 , G06F13/4282
Abstract: PURPOSE: A bus system is provided to transmit write address and write data through a single channel from master to slave, thereby offering a bus system with enhanced integration. CONSTITUTION: A master(100) internally transmits write data through a first write data channel. The master internally transmits an address through a first address channel. A bus(300) transmits the write data and the write address from the master to a slave through a single channel. The master includes a master block and a master bridge. The master bridge receives the address through the first address channel.
Abstract translation: 目的：提供总线系统，通过单个通道从主机传输写入地址和写入数据，从而为总线系统提供增强的集成。 构成：主机（100）通过第一个写入数据通道内部发送写入数据。 主机通过第一个地址通道内部发送一个地址。 总线（300）通过单个通道将写入数据和写入地址从主机发送到从机。 主人包括一个主块和一个主桥。 主桥通过第一个地址通道接收地址。
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公开(公告)号：KR102206313B1
公开(公告)日：2021-01-22
申请号：KR1020140014260
申请日：2014-02-07
Applicant: 삼성전자주식회사
Abstract: 본발명은시스템인터커넥트에관한것이다. 본발명의시스템인터커넥트는, 제1 클럭에기반하여제어신호들을전송하도록구성되는제1 채널, 그리고제2 클럭에기반하여데이터신호들을전송하도록구성되는제2 채널로구성된다. 제1 채널및 제2 채널은미리정해진범위의비순서성을허용한다. 비순서성은, 제어신호들의순서및 제어신호들에각각대응하는데이터신호들의순서가서로다른것이다.
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Patent Agency Ranking
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公开(公告)号：KR101861769B1
公开(公告)日：2018-05-29
申请号：KR1020110123872
申请日：2011-11-24
Applicant: 삼성전자주식회사
IPC: G06F1/00
CPC classification number: G06F13/405
Abstract: 본발명에따른비동기식브릿지는, 마스터 IP로부터전송되는라이트유효신호및 입력데이터를수신하고, 상기라이트유효신호에기초하여생성되는라이트어드레스를출력하고, 상기라이트어드레스에기초하여상기입력데이터를다수의메모리셀에순차적으로저장하고, 리드어드레스에기초하여상기저장된데이터를순차적으로출력하는송신부; 및슬레이브 IP로부터전송되는리드준비신호를수신하고, 상기라이트어드레스및 상기리드어드레스에기초하여상기다수의메모리셀의유효성여부를판단하고, 상기판단결과에기초하여리드유효신호및 데이터를출력하는수신부를포함한다.
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公开(公告)号：KR1020110058575A
公开(公告)日：2011-06-01
申请号：KR1020090115414
申请日：2009-11-26
Applicant: 삼성전자주식회사
CPC classification number: G06F13/405
Abstract: PURPOSE: A bandwidth synchronization circuit and bandwidth synchronization method thereof in a data processing system are provided to improve the operation performance of SOC(System-On-Chip) and to reduce a manufacturing cost of the data processing system by minimizing synchronization bottleneck between a CPU and a bus. CONSTITUTION: An upsizer(200) is composed of a synchronizing packer and a sync unpaker according to processor clock. A synchronizing down unit(250) is connected to the upsizer in response to the bus clock of low frequency. The synchronizing packer performs synchronization packing about a write address, data, and response channel. The synchronizing packer performs synchronization packing about a read address and data channel.
Abstract translation: 目的：提供数据处理系统中的带宽同步电路和带宽同步方法，以提高SOC（片上系统）的运行性能，并通过最小化数据处理系统的同步瓶颈来降低数据处理系统的制造成本 和一辆公共汽车。 构成：根据处理器时钟，升压器（200）由同步封隔器和同步打包器组成。 响应于低频的总线时钟，同步下降单元（250）连接到升压器。 同步封隔器对写入地址，数据和响应通道执行同步打包。 同步打包器对读地址和数据通道执行同步打包。
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公开(公告)号：KR101699781B1
公开(公告)日：2017-01-26
申请号：KR1020100102008
申请日：2010-10-19
Applicant: 삼성전자주식회사
IPC: G06F13/16
CPC classification number: G06F13/4217 , G06F2213/0038
Abstract: 본발명에따른시스템온 칩은, 마스터장치, 상기마스터장치의요청에응답하여데이터를공급하는복수의슬레이브장치들, 그리고상기복수의슬레이브장치들로부터전달되는복수의응답데이터들을상기마스터장치가요청한순서에따라상기마스터장치에제공하는인터커넥터를포함하되, 상기인터커넥터는상기요청데이터를상기마스터장치의동작특성에따른우선순위로중재한다.
Abstract translation: 片上系统半导体器件包括被配置为发出具有事务ID的请求的第一主设备，被配置为响应于该请求而提供数据的多个从设备，以及互连器，被配置为包括从接口， 向所述主接口提供所述请求，并且基于所述第一主设备的操作特性向所述第一主设备提供响应数据。 将从多个从设备提供的多个响应数据传送到主设备的互连器的仲裁方法包括基于主设备的操作特性选择多个仲裁模式中的一个; 并以与所选仲裁模式对应的传送优先级确定的顺序传送响应数据。
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