公开(公告)号：KR1020030024215A

公开(公告)日：2003-03-26

申请号：KR1020010057266

申请日：2001-09-17

Applicant: 삼성전자주식회사

Inventor： 이영기 ,  강성우 ,  지형태

IPC: H01L21/76

Abstract: PURPOSE: A method for forming a trench isolation layer of an SOI substrate is provided to prevent the increase of leakage current by forming a trench isolation layer without a bending phenomenon of a semiconductor layer. CONSTITUTION: A substrate(130) including a base layer(110), a buried oxide layer(115), and a semiconductor layer(120) is prepared. A trench(150) is formed within the semiconductor layer(120) in order to define an active region of the semiconductor layer(120). A thermal oxidation process for the remaining semiconductor layer(120) of a bottom portion of the trench(150) is performed. A thermal oxide layer(155) is formed on an inner wall and the bottom of the trench(150) by performing the thermal process. An insulating layer is formed thereon in order to bury the trench(150) including the thermal oxide layer(155). An isolation layer(180) including the thermal oxide layer(155), a nitride layer liner pattern(165a), and an oxide layer pattern(170a) is formed within the trench(150).

Abstract translation: 目的：提供一种用于形成SOI衬底的沟槽隔离层的方法，以通过形成不具有半导体层弯曲现象的沟槽隔离层来防止漏电流的增加。 构成：制备包括基底层（110），掩埋氧化物层（115）和半导体层（120）的衬底（130）。 为了限定半导体层（120）的有源区，在半导体层（120）内形成沟槽（150）。 执行用于沟槽（150）的底部的剩余半导体层（120）的热氧化工艺。 通过进行热处理，在内壁和沟槽（150）的底部上形成热氧化物层（155）。 在其上形成绝缘层以便埋入包括热氧化物层（155）的沟槽（150）。 在沟槽（150）内形成包括热氧化物层（155），氮化物层衬垫图案（165a）和氧化物层图案（170a）的隔离层（180）。

公开(公告)号：KR1020080013576A

公开(公告)日：2008-02-13

申请号：KR1020060075265

申请日：2006-08-09

Applicant: 삼성전자주식회사

Inventor： 지형태 ,  박영혜 ,  이승록 ,  박경채

IPC: H01L21/336

Abstract: A method for fabricating a semiconductor integrated circuit device is provided to reduce the process time and the manufacture cost by not performing a photolithography process using a mask when a gate electrode is formed. A high concentration impurity region(104) of a first conductive type is formed on a partial region of a semiconductor substrate(100). A low concentration impurity of a first conductive type is implanted into the entire surface of the semiconductor substrate to form a well(106) of a first conductive type. A trench(110) is formed on the semiconductor substrate. A gate dielectric is conformally formed in the trench. A polysilicon is formed to gap-fill the trench. The polysilicon is formed to form a gate electrode(130). A high concentration impurity of a second conductive type is implanted into the semiconductor substrate to form a source region(140). Before the high concentration impurity of a first conductive type is implanted into the partial region of the semiconductor substrate, a low concentration epi layer(102) of a second conductive type is grown on the semiconductor substrate.

Abstract translation: 提供一种制造半导体集成电路器件的方法，通过在形成栅电极时不使用掩模进行光刻处理来减少处理时间和制造成本。 在半导体衬底（100）的部分区域上形成第一导电类型的高浓度杂质区（104）。 将第一导电类型的低浓度杂质注入到半导体衬底的整个表面中以形成第一导电类型的阱（106）。 沟槽（110）形成在半导体衬底上。 栅极电介质在沟槽中共形地形成。 形成多晶硅以间隙填充沟槽。 形成多晶硅以形成栅电极（130）。 将第二导电类型的高浓度杂质注入到半导体衬底中以形成源区（140）。 在将第一导电类型的高浓度杂质注入半导体衬底的部分区域之前，在半导体衬底上生长第二导电类型的低浓度外延层（102）。

公开(公告)号：KR1020050119409A

公开(公告)日：2005-12-21

申请号：KR1020040044491

申请日：2004-06-16

Applicant: 삼성전자주식회사

Inventor： 지형태 ,  이승록 ,  손기황

IPC: H01L29/78

CPC classification number: H01L29/66712 ,  H01L27/0928 ,  H01L29/4236 ,  H01L29/7802

Abstract: 소오스-드레인 사이의 전류량을 증대시킬 수 있는 전력 소자 및 그 제조방법을 개시한다. 개시된 본 발명의 전력 소자는, 저면에 제 1 도전형의 드레인 영역을 포함하고 있는 제 1 도전형 반도체 기판, 상기 반도체 기판 상에 형성되며, 일정 간격 이격되어진 다수의 게이트 전극, 상기 게이트 전극 사이의 반도체 기판 영역에 제 1 깊이를 가지며 형성되는 제 2 도전형 웰, 상기 게이트 전극 사이의 제 2 도전형 웰 영역에 형성되며, 상기 제 1 깊이보다는 얕은 제 2 깊이를 가지며 형성되는 제 1 도전형 소오스 영역, 및 상기 소오스 영역의 소정 부분에 형성되는 제 2 도전형의 벌크 영역을 포함하며, 상기 소오스 영역의 표면에 소정 깊이의 그루브가 형성되어 있다.

公开(公告)号：KR100421048B1

公开(公告)日：2004-03-04

申请号：KR1020010055064

申请日：2001-09-07

Applicant: 삼성전자주식회사

Inventor： 남동균 ,  신헌종 ,  지형태

IPC: H01L21/334

CPC classification number: H01L21/76895 ,  H01L21/31116 ,  H01L21/76897 ,  H01L29/66409 ,  H01L29/80

Abstract: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.

Abstract translation: 提供了具有局部互连层的半导体器件及其制造方法。 局部互连层形成在隔离层和结层上的层间介质（ILD）层中，用于覆盖半导体衬底，隔离层和栅极图案。 在局部互连层下方形成具有至少一个用于防止隔离层的蚀刻的层的蚀刻停止器图案。 当形成局部互连层时，可以包括具有至少一个用于防止隔离层的蚀刻的层的蚀刻终止层图案，由此防止由蚀刻隔离层引起的漏电流，改善半导体器件的电特性，以及 提高制造半导体器件的工艺的成品率。

公开(公告)号：KR1020050011388A

公开(公告)日：2005-01-29

申请号：KR1020030050478

申请日：2003-07-23

Applicant: 삼성전자주식회사

Inventor： 지형태 ,  이승록

IPC: H01L21/336

Abstract: PURPOSE: A semiconductor device with a trench gate structure and a forming method thereof are provided to increase transfer rate of a gate signal by improving conductivity of a conductive line using a polysilicon layer and a metallic silicide pattern as the conductive line. CONSTITUTION: A trench is formed in a substrate(10). A gate oxide layer(16) is formed along the entire inner surface of the trench. A trench gate line(18) is filled in the trench. An insulating pattern(20) for exposing partially the trench gate line to the outside is formed thereon. A polysilicon pattern(22a) is formed on the insulating pattern to contact electrically the trench gate line. A conductive line(26) is completed by forming a metallic silicide pattern(24a) on the polysilicon pattern.

Abstract translation: 目的：提供具有沟槽栅极结构的半导体器件及其形成方法，以通过使用多晶硅层和金属硅化物图案作为导线改善导电线的导电率来提高栅极信号的传输速率。 构成：在衬底（10）中形成沟槽。 沿着沟槽的整个内表面形成栅氧化层（16）。 沟槽栅极线（18）填充在沟槽中。 在其上形成用于将沟槽栅极线部分地暴露于外部的绝缘图案（20）。 在绝缘图案上形成多晶硅图案（22a）以与沟槽栅极线电接触。 通过在多晶硅图案上形成金属硅化物图案（24a）来完成导线（26）。

公开(公告)号：KR100684199B1

公开(公告)日：2007-02-20

申请号：KR1020050109250

申请日：2005-11-15

Applicant: 삼성전자주식회사

Inventor： 지형태 ,  이승록

IPC: H01L27/06

Abstract: A power semiconductor device and its manufacturing method are provided to reduce on-resistance of the power semiconductor device by shortening a channel of a current flowing through a substrate. A first conductive-type drift region(60) of low concentration is formed on a front of a first conductive-type substrate(50). A second conductive-type body region(70) is formed on a surface of the drift region. A first conductive-type source region(74) is formed in the body region. A drain electrode(78) is formed on a rear surface of the substrate and has an extended part to a predetermined depth of the substrate. A trench(80) is formed on the rear surface of the substrate. The drain electrode is extended to be gap-filled in the trench.

Abstract translation: 提供功率半导体器件及其制造方法，以通过缩短流经衬底的电流的沟道来减小功率半导体器件的导通电阻。 在第一导电型衬底（50）的正面上形成低浓度的第一导电型漂移区（60）。 第二导电型体区（70）形成在漂移区的表面上。 第一导电型源极区域（74）形成在本体区域中。 漏电极（78）形成在衬底的后表面上并具有延伸到衬底的预定深度的部分。 沟槽（80）形成在衬底的后表面上。 漏电极延伸以在沟槽中间隙填充。

公开(公告)号：KR1020030027377A

公开(公告)日：2003-04-07

申请号：KR1020010060553

申请日：2001-09-28

Applicant: 삼성전자주식회사

Inventor： 지형태 ,  신헌종

IPC: H01L21/76

Abstract: PURPOSE: A method for fabricating a semiconductor device using a salicide blocking layer in a main chip part is provided to prevent a leakage current between a local interconnection and a lower substrate by using the salicide blocking layer in every portion of the main chip except the upper portion of an active region and a gate. CONSTITUTION: A salicide blocking layer material having etch selectivity different from that of a layer in an isolation region is deposited on the front surface of a semiconductor substrate(100) having a source/drain(110) and a gate(120). The salicide blocking layer material is etched to expose the active region(105) and the gate in the main chip so that a salicide blocking layer(130) is formed. An etch stop layer(140) is formed on the front surface of the semiconductor substrate having the salicide blocking layer. The salicide blocking layer is etched to form the local interconnection.

Abstract translation: 目的：提供一种在主芯片部分中使用硅化物阻挡层制造半导体器件的方法，以通过在主芯片的除了上部的芯片的每个部分中使用自对准硅化物阻挡层来防止局部互连和下基板之间的漏电流 有源区域和栅极的一部分。 构成：在具有源极/漏极（110）和栅极（120）的半导体衬底（100）的前表面上沉积具有与隔离区域中的层的蚀刻选择性不同的蚀刻选择性的自对准硅化物阻挡层材料。 蚀刻硅化物阻挡层材料以暴露主芯片中的有源区（105）和栅极，从而形成自对准硅化物阻挡层（130）。 在具有硅化物阻挡层的半导体衬底的前表面上形成蚀刻停止层（140）。 蚀刻硅化物阻挡层以形成局部互连。

公开(公告)号：KR1020030021689A

公开(公告)日：2003-03-15

申请号：KR1020010055064

申请日：2001-09-07

Applicant: 삼성전자주식회사

Inventor： 남동균 ,  신헌종 ,  지형태

IPC: H01L21/334

CPC classification number: H01L21/76895 ,  H01L21/31116 ,  H01L21/76897 ,  H01L29/66409 ,  H01L29/80

Abstract: PURPOSE: A semiconductor device having a local interconnection layer is provided to prevent a leakage current caused by etching an isolation layer by forming at least one etch stop layer pattern for preventing the isolation layer from being etched in forming the local interconnection layer. CONSTITUTION: The isolation layer(102) defines an active region of a semiconductor substrate(100) under both sides of a gate pattern(104). An adhesion layer(110) is formed in the semiconductor substrate under both sides of the gate pattern. The semiconductor substrate, the isolation layer and the gate pattern are covered with an interlayer dielectric. The local interconnection layer is formed on the interlayer dielectric on the isolation layer and the adhesion layer. At least one etch stop layer pattern for preventing the isolation layer of the local interconnection layer from being etched is formed.

Abstract translation: 目的：提供具有局部互连层的半导体器件，以防止通过形成至少一个蚀刻停止层图案来蚀刻隔离层而引起的漏电流，以防止隔离层在形成局部互连层时被蚀刻。 构成：隔离层（102）在栅极图案（104）的两侧限定半导体衬底（100）的有源区。 在栅极图案的两侧的半导体衬底中形成粘合层（110）。 半导体衬底，隔离层和栅极图案被层间电介质覆盖。 局部互连层形成在隔离层和粘合层上的层间电介质上。 形成用于防止局部互连层的隔离层被蚀刻的至少一个蚀刻停止层图案。