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公开(公告)号：KR1020140112771A
公开(公告)日：2014-09-24
申请号：KR1020130027261
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11582 , H01L21/76224 , H01L27/11551 , H01L27/11565 , H01L29/7889 , H01L21/2018 , H01L21/823487 , H01L27/11578 , H01L29/7926
Abstract: A vertical semiconductor element includes a semiconductor pattern, including a first foreign matter area doped with a first conductive foreign matter and having first foreign matter concentration, in a substrate. A second foreign matter area, doped with the first conductive foreign matter and having second foreign matter concentration, is included in a part of the substrate touching the semiconductor pattern. A filler structure including a channel pattern is included in the semiconductor pattern. Word line structures horizontally, extended while surrounding sides of the filler structure and the semiconductor pattern and provided to a gate of a transistor, are included. A third foreign matter area, doped with a second conductive foreign matter which is the opposite to the first conductive foreign matter and provided to a common source line, is included in a part of the substrate which is adjacent to a side end part of the word line structures. A fourth foreign matter area, having third foreign matter concentration lower than the first and second foreign matter concentration, is included between first foreign matter areas and between the first and third foreign matter areas. The vertical semiconductor element reduces the distribution of an electric property.
Abstract translation: 垂直半导体元件包括在衬底中包括掺杂有第一导电异物并且具有第一异物浓度的第一异质区域的半导体图案。 掺杂有第一导电异物并且具有第二异物浓度的第二异物区域包括在接触半导体图案的基板的一部分中。 包括沟道图案的填充结构包括在半导体图案中。 包括字线结构水平地延伸，而填充结构的周边和半导体图案被提供到晶体管的栅极。 掺杂有与第一导电异物相反并提供给公共源极线的第二导电异物的第三异物区域包括在与该字的侧端部分相邻的衬底的一部分中 线结构。 具有第一异物浓度低于第一和第二异物浓度的第三异物浓度的第四异物区域被包括在第一异物区域之间以及第一和第三异物区域之间。 垂直半导体元件减小了电性能的分布。
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公开(公告)号：KR101539404B1
公开(公告)日：2015-07-27
申请号：KR1020100001757
申请日：2010-01-08
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/42336 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/42352 , H01L29/7881 , H01L29/792
Abstract: 비휘발성기억소자및 그제조방법을제공한다. 기판상에터널절연패턴이제공되고, 터널절연패턴상에플로팅게이트가제공되고, 플로팅게이트상에전하트랩사이트를갖는플로팅게이트캡이제공되고, 플로팅게이트캡 상에게이트절연패턴이제공되고, 게이트절연패턴상에컨트롤게이트가제공된다.
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公开(公告)号：KR101533447B1
公开(公告)日：2015-07-02
申请号：KR1020090093315
申请日：2009-09-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/4234 , H01L27/11521 , H01L27/11568 , H01L29/42336 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/7883 , H01L29/792
Abstract: 반도체소자가제공된다. 반도체소자는전하저장패턴을덮되, 전하저장패턴의모서리영역을덮는블로킹막의부분의두께가나머지부분의두께보다두꺼워, 전하저장패턴의모서리영역에전계가집중되는것이완화될수 있다.
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公开(公告)号：KR1020110081547A
公开(公告)日：2011-07-14
申请号：KR1020100001757
申请日：2010-01-08
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/42336 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/42352 , H01L29/7881 , H01L29/792 , H01L21/823437
Abstract: 비휘발성기억소자및 그제조방법을제공한다. 기판상에터널절연패턴이제공되고, 터널절연패턴상에플로팅게이트가제공되고, 플로팅게이트상에전하트랩사이트를갖는플로팅게이트캡이제공되고, 플로팅게이트캡 상에게이트절연패턴이제공되고, 게이트절연패턴상에컨트롤게이트가제공된다.
Abstract translation: 目的：提供一种非易失性存储器件及其形成方法，以通过在浮动栅极和栅极绝缘膜之间提供浮动栅极帽并且由于电场集中而抑制漏电流来提高耐久性。 构成：在非易失性存储器件及其形成方法中，向衬底提供隧道绝缘图案。 在隧道绝缘图案上提供浮动栅极（123）。 浮动盖帽（133）被提供到浮动闸门并具有电荷捕获位置。 栅极绝缘图案（152）设置到浮动栅极盖。 控制栅极（162）设置在栅极绝缘图案上。
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公开(公告)号：KR1020100109786A
公开(公告)日：2010-10-11
申请号：KR1020090028219
申请日：2009-04-01
Applicant: 삼성전자주식회사
Inventor： 파이루신알버트
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11568 , H01L21/28052 , H01L21/28282 , H01L21/67075 , H01L21/76224
Abstract: PURPOSE: A method for manufacturing a memory device is provided to secure a trapping film for electric charges with a uniform thickness by eliminating the exposed part of a pre-trapping film for electric charges through an isotropic etching process. CONSTITUTION: A tunnel insulating film(140) is formed on a substrate(100). A pre-trapping film for electric charges(154) is formed on the tunnel insulating film. An etching stop film is formed to expose a part of the pre-trapping film for the electric charges. The exposed part of the pre-trapping film for the electric charges is eliminated to form a trapping film for the electric charges with a uniform thickness. A dielectric film is formed on the trapping film for the electric charges. A gate is formed on the dielectric film.
Abstract translation: 目的：提供一种用于制造存储器件的方法，通过各向同性蚀刻工艺消除用于电荷的预捕获膜的暴露部分，从而将均匀厚度的电荷捕获膜固定。 构成：在衬底（100）上形成隧道绝缘膜（140）。 在隧道绝缘膜上形成用于电荷的预捕获膜（154）。 形成蚀刻停止膜以暴露用于电荷的预捕获膜的一部分。 消除用于电荷的预捕获膜的暴露部分，以形成均匀厚度的电荷的捕获膜。 在用于电荷的捕获膜上形成介电膜。 在电介质膜上形成栅极。
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Patent Agency Ranking
公开(公告)号：KR1020090022120A
公开(公告)日：2009-03-04
申请号：KR1020070087205
申请日：2007-08-29
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11521 , H01L21/28141 , H01L21/28273 , H01L21/31144
Abstract: A non-volatile memory device and a manufacturing method thereof are provided to reduce the intensity of the electric field generated by a control gate electrode and a substrate by forming the narrower control gate electrode than the floating gate electrode. A tunnel insulating layer(102) is formed on a substrate(100). A floating gate electrode(118) is formed on the tunnel insulating layer and has a first line width. A dielectric pattern(114) is formed on the floating gate electrode and has a second line width smaller than the first line width. The control gate electrode(112) is formed on the dielectric pattern and has a third line width smaller than the first line width. The second line width is equal to the third line width. A spacer(116) is formed on the side of the control gate electrode and the dielectric pattern. The mask is formed on the control gate electrode and has the line width equal to the third line width.
Abstract translation: 提供了一种非易失性存储器件及其制造方法，通过形成比浮置栅电极更窄的控制栅电极来减小由控制栅电极和衬底产生的电场的强度。 在衬底（100）上形成隧道绝缘层（102）。 在隧道绝缘层上形成浮栅电极（118），具有第一线宽。 介电图案（114）形成在浮置栅电极上，并且具有小于第一线宽的第二线宽。 控制栅电极（112）形成在电介质图案上，并且具有小于第一线宽的第三线宽度。 第二行宽度等于第三行宽。 间隔物（116）形成在控制栅电极和电介质图案的一侧。 掩模形成在控制栅电极上，并且线宽等于第三线宽。
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公开(公告)号：KR102054226B1
公开(公告)日：2019-12-10
申请号：KR1020130027261
申请日：2013-03-14
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
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公开(公告)号：KR1020120057794A
公开(公告)日：2012-06-07
申请号：KR1020100119297
申请日：2010-11-29
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11521 , H01L21/28273 , H01L21/764 , H01L21/7682 , H01L27/11519 , H01L21/28141 , H01L21/76205
Abstract: PURPOSE: A non-volatile memory device and a manufacturing method thereof are provide to effectively reduce parasitic capacitance and channel coupling by forming an air gap between word lines. CONSTITUTION: A plurality of gate structures(200) which is separated is located on a substrate(100). The plurality of gate structures comprises a tunnel insulating film pattern(110b), a floating gate electrode(120b), and a dielectric layer pattern(160a). A second insulating film pattern(220) is formed between the plurality of gate structures and has a second air gap(222) in inside. An element isolation structure has a first air gap(146) between the plurality of gate structures. The element isolation structure comprises a liner(140a) and a first buried film(142).
Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，通过在字线之间形成气隙来有效地减少寄生电容和沟道耦合。 构成：分离的多个栅极结构（200）位于基板（100）上。 多个栅极结构包括隧道绝缘膜图案（110b），浮栅电极（120b）和电介质层图案（160a）。 第二绝缘膜图案（220）形成在多个栅极结构之间并且在内部具有第二气隙（222）。 元件隔离结构在多个栅极结构之间具有第一气隙（146）。 元件隔离结构包括衬垫（140a）和第一掩埋膜（142）。
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公开(公告)号：KR100869232B1
公开(公告)日：2008-11-18
申请号：KR1020070058235
申请日：2007-06-14
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/115 , H01L27/11521 , H01L21/28052 , H01L21/28273 , H01L21/76838
Abstract: The upper part of a preliminary element isolation film is removed to expose the part of the preliminary element isolation film in the formation of a floating gate. Thereafter, the exposed part of the preliminary floating gate is removed by the isotropic etching process. The memory device includes the substrate(200) including the active area having the protruded shape in the vertical direction; the element isolation film(234) formed between the protruded active area; the tunnel insulating layer(240) formed on the active area of substrate(240); the floating gate(254) which is formed on the tunnel insulating layer with the uniform thickness, and the its part is formed on the element isolation film; the dielectric layer(280) formed on the floating gate; the control gate(290) formed on the dielectric layer.
Abstract translation: 去除初步元件隔离膜的上部，以在浮栅的形成中露出初步元件隔离膜的一部分。 此后，通过各向同性蚀刻工艺去除初步浮栅的露出部分。 存储装置包括：基板（200），其具有在垂直方向上具有突出形状的有源区域; 所述元件隔离膜（234）形成在所述突出的有源区域之间; 形成在基板（240）的有源区上的隧道绝缘层（240）; 形成在厚度均匀的隧道绝缘层上的浮栅（254），其部分形成在元件隔离膜上; 形成在浮栅上的电介质层（280） 形成在电介质层上的控制栅极（290）。
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公开(公告)号：KR1020150060144A
公开(公告)日：2015-06-03
申请号：KR1020130144231
申请日：2013-11-26
Applicant: 삼성전자주식회사
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/3459 , H01L27/11582
Abstract: 기판및 기판에수직한방향으로기판상에순차적으로적층되는제1 내지제n(n은 2이상의정수) 워드라인을포함하는비휘발성메모리장치의동작방법에있어서, 제1 내지제n 워드라인중에서기판에인접하여형성되는제1 내지제k(k는 n보다작은양의정수) 워드라인에제1 내지제k 워드라인전압을각각인가하고, 제1 내지제n 워드라인중에서제1 내지제k 워드라인의상부에형성되는제(k+1) 내지제n 워드라인에제1 내지제k 워드라인전압보다낮은제(k+1) 내지제n 워드라인전압을각각인가하고, 기판에제1 내지제n 워드라인전압보다높은소거전압을인가한다. 비휘발성메모리장치의동작방법은소거상태에있는메모리셀들의문턱전압산포를감소시킨다.
Abstract translation: 提供一种操作非易失性存储器件的方法，该非易失性存储器件包括从第一至第n（n为2以上的整数）的衬底和字线，在与衬底垂直的方向依次层叠在衬底上。 该方法包括：从第一到第k个的字线单独地施加字线电压到从第一到第九字的字线之间的从第一到第k（k个小于n的正整数）相邻形成的字线的字线 ; 分别将字线电压从（k + 1）到第n ^ th，低于从第一到第k ^的字线电压到从（k + 1）^到n ^ th的字线形成在 从第一个到第n个字的字线的第一到第k个的字线; 并且在基板上施加高于字线电压的消光电压从第一到第n。 操作非易失性存储器件的方法降低了消光状态下的存储器单元的阈值电压分布。
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