公开(公告)号：KR1020080036846A

公开(公告)日：2008-04-29

申请号：KR1020060103629

申请日：2006-10-24

Applicant: 삼성전자주식회사

Inventor： 엄중섭 ,  박세종 ,  한현숙

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L21/28141 ,  H01L21/28273 ,  H01L21/823437 ,  H01L29/66825

Abstract: A flash memory device having a split gate structure and a method for manufacturing the same are provided to prevent degradation of a gate dielectric by minimizing a mechanical stress applied to the gate dielectric. A floating gate(110a) is provided on an active region of a semiconductor substrate(100). A lower width of the floating gate is greater than an upper width thereof. A first gate dielectric(105a) is disposed between the floating gate and the adjacent active region. A control gate(130) crosses the active region adjacent to the floating gate and partially covers the floating gate. Second gate dielectrics(125) are disposed between the control gate and the floating gate, and between the control gate and the active region. The floating gate has a round sidewall. An upper region of the floating gate has a vertical sidewall. A lower region of the floating gate has a round sidewall. An upper surface of the floating gate is a concave shape.

Abstract translation: 提供一种具有分割栅极结构的闪存器件及其制造方法，以通过使施加到栅极电介质的机械应力最小化来防止栅极电介质的劣化。 浮置栅极（110a）设置在半导体衬底（100）的有源区上。 浮动栅极的较低宽度大于其上部宽度。 第一栅极电介质（105a）设置在浮置栅极和相邻有源区域之间。 控制栅极（130）跨越与浮动栅极相邻的有源区域并且部分地覆盖浮置栅极。 第二栅极电介质（125）设置在控制栅极和浮动栅极之间以及控制栅极和有源区域之间。 浮动门具有圆形侧壁。 浮动栅极的上部区域具有垂直侧壁。 浮动栅极的下部区域具有圆形侧壁。 浮栅的上表面是凹形。

公开(公告)号：KR100772905B1

公开(公告)日：2007-11-05

申请号：KR1020060107326

申请日：2006-11-01

Applicant: 삼성전자주식회사

Inventor： 양봉길 ,  엄중섭 ,  주섭열 ,  박세종 ,  한현숙

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/7885 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory device and a manufacturing method thereof are provided to suppress a reverse tunneling phenomenon by increasing a slant angle between a lower portion of a floating gate electrode and a semiconductor substrate. A non-volatile memory device includes a semiconductor substrate(100), a floating gate electrode(132), and a control gate electrode(150). The floating gate electrode has an acute tip at an upper portion thereof. An angle between the semiconductor substrate and the upper portion of the floating gate electrode is smaller than the angle between the semiconductor substrate and a lower portion of the floating gate electrode. The control gate electrode is insulated from the floating gate electrode and arranged to face at least a portion of the floating gate electrodes.

Abstract translation: 提供了一种非易失性存储器件及其制造方法，以通过增加浮置栅电极的下部与半导体衬底之间的倾斜角来抑制反向隧道现象。 非易失性存储器件包括半导体衬底（100），浮栅电极（132）和控制栅电极（150）。 浮栅电极在其上部具有尖锐尖端。 半导体衬底与浮栅电极的上部之间的角度小于半导体衬底与浮栅电极的下部之间的角度。 控制栅极电极与浮置栅电极绝缘并且布置成面对至少一部分浮栅电极。