公开(公告)号：KR100772905B1

公开(公告)日：2007-11-05

申请号：KR1020060107326

申请日：2006-11-01

Applicant: 삼성전자주식회사

Inventor： 양봉길 ,  엄중섭 ,  주섭열 ,  박세종 ,  한현숙

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/7885 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory device and a manufacturing method thereof are provided to suppress a reverse tunneling phenomenon by increasing a slant angle between a lower portion of a floating gate electrode and a semiconductor substrate. A non-volatile memory device includes a semiconductor substrate(100), a floating gate electrode(132), and a control gate electrode(150). The floating gate electrode has an acute tip at an upper portion thereof. An angle between the semiconductor substrate and the upper portion of the floating gate electrode is smaller than the angle between the semiconductor substrate and a lower portion of the floating gate electrode. The control gate electrode is insulated from the floating gate electrode and arranged to face at least a portion of the floating gate electrodes.

Abstract translation: 提供了一种非易失性存储器件及其制造方法，以通过增加浮置栅电极的下部与半导体衬底之间的倾斜角来抑制反向隧道现象。 非易失性存储器件包括半导体衬底（100），浮栅电极（132）和控制栅电极（150）。 浮栅电极在其上部具有尖锐尖端。 半导体衬底与浮栅电极的上部之间的角度小于半导体衬底与浮栅电极的下部之间的角度。 控制栅极电极与浮置栅电极绝缘并且布置成面对至少一部分浮栅电极。

公开(公告)号：KR1020080014483A

公开(公告)日：2008-02-14

申请号：KR1020060076270

申请日：2006-08-11

Applicant: 삼성전자주식회사

Inventor： 주섭열 ,  노재윤

IPC: H01L21/8242 ,  H01L27/04

CPC classification number: H01L28/91 ,  H01L28/87

Abstract: A semiconductor device having metal/an insulating film/a metal capacitor and a method for forming the same are provided to prevent generation of a crack of the dielectric film pattern by reducing mechanical stress of a dielectric film pattern concentrated in an edge adjacent to a side wall of a first interlayer insulating film. A semiconductor device comprises a lower electrode(12), a first interlayer insulating film(14), a dielectric film pattern(18a), and an upper electrode(20a,22a). The lower electrode is formed on a substrate(10). The first interlayer insulating film is formed on the substrate having the lower electrode, and has an opening(16a) exposing the lower electrode. The dielectric film pattern is formed inside the opening conformally. The upper electrode is formed on the dielectric film. A side wall of the first interlayer insulating film defining the opening has a slope.

Abstract translation: 提供具有金属/绝缘膜/金属电容器的半导体器件及其形成方法，以通过降低集中在与侧面相邻的边缘中的电介质膜图案的机械应力来防止电介质膜图案的裂纹的产生 第一层间绝缘膜的壁。 半导体器件包括下电极（12），第一层间绝缘膜（14），电介质膜图案（18a）和上电极（20a，22a）。 下电极形成在基板（10）上。 第一层间绝缘膜形成在具有下电极的基板上，并且具有暴露下电极的开口（16a）。 电介质膜图案形成在开口的内侧。 上电极形成在电介质膜上。 限定开口的第一层间绝缘膜的侧壁具有斜率。

公开(公告)号：KR1020070077670A

公开(公告)日：2007-07-27

申请号：KR1020060007378

申请日：2006-01-24

Applicant: 삼성전자주식회사

Inventor： 조찬형 ,  박형무 ,  주섭열 ,  김경우

IPC: H01L21/28

CPC classification number: H01L21/76807 ,  H01L21/76829 ,  H01L21/76877

Abstract: A method for fabricating a semiconductor memory device and the semiconductor memory device fabricated by the same are provided to decrease resistance of via holes by increasing overlap margin between the via holes and a trench. A first interlayer dielectric(114), an etch stop layer and a second interlayer dielectric(118) are sequentially formed on a lower wiring(110), and then are partially etched to form via holes(132,134) exposing an upper surface of the lower wiring. A sacrificial layer(140) is formed to fill a portion of the via holes. The second interlayer dielectric formed on the via hole is etched to expand an upper portion of the via hole. After removing the sacrificial layer, a trench which is connected to the via hole is formed. An upper wiring is formed to fill the via holes and the trench.

Abstract translation: 提供一种用于制造半导体存储器件的方法和由其制造的半导体存储器件，以通过增加通孔和沟槽之间的重叠裕度来降低通孔的电阻。 第一层间电介质（114），蚀刻停止层和第二层间电介质（118）依次形成在下布线（110）上，然后被部分蚀刻以形成露出下部布线（110）的上表面的通孔（132,134） 接线。 形成牺牲层（140）以填充通孔的一部分。 在通孔上形成的第二层间电介质被蚀刻以扩大通孔的上部。 在去除牺牲层之后，形成连接到通孔的沟槽。 形成上部布线以填充通孔和沟槽。

公开(公告)号：KR1020080080795A

公开(公告)日：2008-09-05

申请号：KR1020070020973

申请日：2007-03-02

Applicant: 삼성전자주식회사

Inventor： 노재윤 ,  주섭열

IPC: H01L27/108 ,  H01L27/04

CPC classification number: H01L28/40 ,  H01L27/10855 ,  H01L28/91

Abstract: A MIM(Metal-Insulator-Metal) capacitor having a spacer type dielectric layer and a manufacturing method thereof are provided to reduce physical stress applied to the spacer type dielectric layer in a planarization process. A lower electrode(120) is arranged on a semiconductor substrate(105). An interlayer dielectric(125) is formed to cover the lower electrode and the semiconductor substrate and includes an opening(130) for exposing a predetermined region of the lower electrode. A spacer(135) is formed on a sidewall of the opening. The spacer includes an external sidewall contacting the sidewall of the opening and an internal sidewall facing the external sidewall. The spacer includes an inclined profile to increase a width of a space surrounded by the internal sidewall in an upper direction. A dielectric layer(140) is formed to cover the internal sidewall of the spacer and an upper surface of the lower electrode. An upper electrode(150) is formed to cover the dielectric layer.

Abstract translation: 提供具有间隔型电介质层的MIM（金属 - 绝缘体 - 金属）电容器及其制造方法，以减少在平坦化处理中施加到间隔型电介质层的物理应力。 下电极（120）布置在半导体衬底（105）上。 形成层间电介质（125）以覆盖下电极和半导体衬底，并且包括用于暴露下电极的预定区域的开口（130）。 间隔物（135）形成在开口的侧壁上。 间隔件包括接触开口的侧壁的外侧壁和面向外侧壁的内侧壁。 间隔件包括倾斜轮廓，以在上方向上增加由内侧壁围绕的空间的宽度。 形成绝缘层（140）以覆盖间隔物的内侧壁和下电极的上表面。 形成上电极（150）以覆盖电介质层。

公开(公告)号：KR1020060083505A

公开(公告)日：2006-07-21

申请号：KR1020050004225

申请日：2005-01-17

Applicant: 삼성전자주식회사

Inventor： 주섭열 ,  박형무

IPC: H01L27/04

CPC classification number: H01L28/40 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/7687

Abstract: 커패시터 형성방법을 제공한다. 이 방법은 기판 상에 하부전극을 형성하는 단계와, 상기 하부전극 측벽에 커패시터 유전막을 형성하는 단계를 포함한다. 상기 커패시터 유전막의 측벽에 상부전극을 형성하고, 상기 하부전극 및 상기 상부전극에 각각 배선을 연결한다.